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jhauga
234 lines
4.8 KiB
Markdown
234 lines
4.8 KiB
Markdown
# AS6C62256 (32K x 8 SRAM) Emulation Specification
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A technical Markdown specification for **emulating the AS6C62256 / 62256-family static RAM**, suitable for 6502-family emulators, SBC simulators, and memory subsystem modeling.
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---
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## 1. Scope
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This document specifies functional behavior for emulating:
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* Alliance Memory **AS6C62256**
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* Compatible **62256 (32K x 8) SRAM** devices
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Out of scope:
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* Analog electrical timing margins
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* Bus contention and signal rise/fall times
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* Power consumption characteristics
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---
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## 2. Chip Overview
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### Core Characteristics
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| Feature | Value |
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| -------------- | -------------------- |
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| Memory Type | Static RAM (SRAM) |
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| Capacity | 32,768 bytes (32 KB) |
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| Data Width | 8-bit |
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| Address Width | 15-bit (A0-A14) |
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| Access Type | Asynchronous |
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| Supply Voltage | 5 V (typical) |
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---
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## 3. External Signals (Logical Model)
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| Signal | Direction | Purpose |
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| ------ | --------- | -------------------------- |
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| A0-A14 | Input | Address bus |
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| D0-D7 | I/O | Data bus |
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| CE# | Input | Chip enable (active low) |
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| OE# | Input | Output enable (active low) |
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| WE# | Input | Write enable (active low) |
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> `#` indicates active-low signals.
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---
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## 4. Address Space Mapping
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* Address range: `0x0000-0x7FFF`
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* Address lines select one byte per address
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### Typical 6502 System Mapping Example
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| CPU Address Range | Device |
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| ----------------- | -------------- |
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| `$0000-$7FFF` | AS6C62256 SRAM |
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| `$8000-$FFFF` | ROM / EEPROM |
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---
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## 5. Read and Write Behavior
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### Read Cycle (Logical)
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Conditions:
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* `CE# = 0`
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* `OE# = 0`
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* `WE# = 1`
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Behavior:
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```text
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D[7:0] memory[A]
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```
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If `OE# = 1` or `CE# = 1`, data bus is **high-impedance**.
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---
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### Write Cycle (Logical)
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Conditions:
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* `CE# = 0`
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* `WE# = 0`
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Behavior:
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```text
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memory[A] D[7:0]
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```
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* `OE#` is ignored during writes
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* Write occurs on active WE#
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---
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## 6. Control Signal Priority
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| CE# | WE# | OE# | Result |
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| --- | --- | --- | --------------- |
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| 1 | X | X | Disabled (Hi-Z) |
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| 0 | 0 | X | Write |
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| 0 | 1 | 0 | Read |
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| 0 | 1 | 1 | Hi-Z |
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---
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## 7. Emulator Interface Requirements
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An emulator must expose:
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```text
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read(address) -> byte
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write(address, byte)
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```
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Internal storage:
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```text
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uint8_t ram[32768]
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```
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Address masking:
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```text
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address = address & 0x7FFF
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```
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---
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## 8. Timing Model (Abstracted)
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### Emulation Levels
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| Level | Description |
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| -------------- | ------------------------- |
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| Functional | Instantaneous access |
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| Cycle-based | Access per CPU cycle |
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| Cycle-accurate | Honors enable transitions |
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For most systems, **functional emulation** is sufficient.
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---
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## 9. Power and Data Retention
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* SRAM contents persist as long as power is applied
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* Emulator shall retain contents until explicitly reset
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### Reset Behavior
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* **No automatic clearing** on reset
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* Memory contents undefined unless initialized
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---
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## 10. Bus Contention and Hi-Z Modeling (Optional)
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Optional advanced behavior:
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* Track when SRAM drives the data bus
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* Detect illegal simultaneous writes
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Most emulators may ignore Hi-Z state.
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---
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## 11. Error Conditions
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| Condition | Emulator Response |
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| -------------------- | ----------------------------- |
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| Out-of-range address | Mask or ignore |
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| Read when disabled | Return last bus value or 0xFF |
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| Write when disabled | Ignore write |
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---
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## 12. Integration with 6502 Emulator
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```text
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CPU memory access
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address decode
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if in SRAM range:
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AS6C62256.read/write
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```
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* SRAM access is typically single-cycle
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* No wait states required
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---
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## 13. Testing and Validation
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### Basic Tests
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* Write/read patterns
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* Boundary addresses ($0000, $7FFF)
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* Randomized memory tests
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### Validation Checklist
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* Writes persist
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* Reads return correct values
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* Address wrapping correct
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---
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## 14. Common Mistakes
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| Mistake | Result |
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| --------------------- | --------------------------- |
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| Clearing RAM on reset | Breaks software assumptions |
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| Wrong address mask | Mirrored memory errors |
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| Treating as ROM | Writes ignored |
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---
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## 15. Reference Links
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* [Alliance Memory AS6C62256 Datasheet](https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf)
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* [https://en.wikipedia.org/wiki/Static_random-access_memory](https://en.wikipedia.org/wiki/Static_random-access_memory)
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---
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**Document Scope:** Software emulation of AS6C62256 SRAM
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**Audience:** Emulator developers, retro SBC designers
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**Status:** Stable technical reference
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