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John Haugabook
178 lines
4.1 KiB
Markdown
178 lines
4.1 KiB
Markdown
# AS6C62256 32K x 8 Low-Power CMOS SRAM Specification
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## 1. Overview
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The **AS6C62256** is a **256 Kbit (32K x 8)** low-power CMOS static random-access memory (SRAM) manufactured by Alliance Memory (and second-sourced by others). It is fully compatible with common 28-pin SRAM pinouts and is widely used in **6502**, **Z80**, and other 8-bit microprocessor systems for read/write memory.
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The device offers fast access times, simple control logic, and very low standby power consumption.
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---
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## 2. General Characteristics
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| Feature | Description |
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| ----------------- | --------------------------------- |
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| Memory size | 256 Kbits (32 KB) |
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| Organization | 32,768 x 8 bits |
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| Data bus | 8-bit |
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| Address bus | 15-bit (A0-A14) |
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| Technology | CMOS SRAM |
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| Access time | 55 ns / 70 ns (variant dependent) |
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| Operating voltage | 5 V ± 10% |
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| Standby current | < 1 µA (typical) |
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| Package types | DIP-28, SOJ-28, TSOP-28 |
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---
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## 3. Pin Configuration (Logical)
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### 3.1 Address Pins (A0-A14)
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* Select one of 32,768 memory locations
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* Address must be stable during read or write cycle
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### 3.2 Data Pins (I/O0-I/O7)
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* Bidirectional tri-state data bus
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* High-impedance when not enabled
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### 3.3 Control Pins
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| Pin | Description |
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| --- | -------------------------- |
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| CE# | Chip Enable (active low) |
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| OE# | Output Enable (active low) |
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| WE# | Write Enable (active low) |
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| VCC | +5 V power supply |
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| GND | Ground |
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---
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## 4. Memory Organization
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* Linear address space from `$0000` to `$7FFF`
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* Each address corresponds to one byte (8 bits)
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```text
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Address range: 0000h - 7FFFh
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Data width: 8 bits
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```
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---
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## 5. Read Operation
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### 5.1 Read Cycle Conditions
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| Signal | State |
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| ------ | ----- |
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| CE? | LOW |
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| OE? | LOW |
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| WE? | HIGH |
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* Data becomes valid after access time (tAA)
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* Outputs remain valid while CE? and OE? are LOW
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* Outputs are high-impedance when CE? or OE? is HIGH
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---
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## 6. Write Operation
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### 6.1 Write Cycle Conditions
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| Signal | State |
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| ------ | ----------- |
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| CE? | LOW |
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| OE? | HIGH or LOW |
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| WE? | LOW pulse |
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* Data is written on the rising edge of WE? or CE?
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* Address and data must be stable during write window
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* No internal write delay (true SRAM behavior)
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## 7. Timing Notes (Summary)
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| Parameter | Typical |
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| -------------------- | -------- |
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| Address access (tAA) | 55-70 ns |
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| CE? access (tACE) | 55-70 ns |
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| OE? access (tOE) | 25-35 ns |
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| Write cycle time | ≥ 55 ns |
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---
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## 8. Power Modes
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### 8.1 Active Mode
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* CE? = LOW
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* Normal read/write operation
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### 8.2 Standby Mode
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* CE? = HIGH
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* Data retained
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* Very low power consumption
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---
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## 9. Reset and Power-Up Behavior
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* No reset pin required
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* Data is undefined at power-up
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* Memory contents preserved only while VCC is present
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---
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## 10. Typical System Integration (6502 Example)
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```text
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Mapped at: $0000 - $7FFF
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CE? decoded address
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OE? R/W?
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WE? inverted R/W?
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```
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---
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## 11. Absolute Maximum Ratings (Summary)
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| Parameter | Rating |
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| ------------- | --------------------- |
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| VCC | -0.5 V to +6.5 V |
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| Input voltage | -0.5 V to VCC + 0.5 V |
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| Storage temp | -65 °C to +150 °C |
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## 12. Compatible and Equivalent Devices
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| Device | Notes |
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| --------- | --------------- |
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| AS6C62256 | Alliance Memory |
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| CY62256 | Cypress |
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| HM62256 | Hitachi |
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| KM62256 | Samsung |
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| IS62C256 | ISSI |
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## 13. Common Use Cases
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* Main RAM for 6502 / Z80 systems
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* Video buffers and frame memory
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* Embedded systems requiring fast R/W memory
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* Retrocomputer SBC designs
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## 14. References
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* <https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf>
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* <https://www.futurlec.com/Datasheet/Memory/62256.pdf>
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* <https://www.malinov.com/sergeys-blog/homebrew-notes.html>
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