Austin Clements
f62085100e
The assembly implementations of ladderstep and mul contain register save prologues that are unnecessary in Go because there are no callee save registers in the Go ABI. Remove these prologues, update all SP offsets, and reduce the frame size accordingly. The SP offsets were updated with: python -c 'import sys, re; sys.stdout.write(re.sub(r"(\d+)\(SP\)", lambda m: "%d(SP)" % (int(m.group(1))-YYY), sys.stdin.read()))' where YYY was 64 for mul_amd64.s and 56 for ladderstep_amd64.s. Change-Id: I728948809f479b1c061cc65167dadad651efab31 Reviewed-on: https://go-review.googlesource.com/31580 Reviewed-by: Adam Langley <agl@golang.org> Reviewed-by: Minux Ma <minux@golang.org>
168 lines
2.5 KiB
ArmAsm
168 lines
2.5 KiB
ArmAsm
// Copyright 2012 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// This code was translated into a form compatible with 6a from the public
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// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
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// +build amd64,!gccgo,!appengine
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// func mul(dest, a, b *[5]uint64)
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TEXT ·mul(SB),0,$16-24
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MOVQ dest+0(FP), DI
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MOVQ a+8(FP), SI
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MOVQ b+16(FP), DX
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MOVQ DX,CX
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MOVQ 24(SI),DX
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IMUL3Q $19,DX,AX
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MOVQ AX,0(SP)
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MULQ 16(CX)
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MOVQ AX,R8
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MOVQ DX,R9
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MOVQ 32(SI),DX
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IMUL3Q $19,DX,AX
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MOVQ AX,8(SP)
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MULQ 8(CX)
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ADDQ AX,R8
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ADCQ DX,R9
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MOVQ 0(SI),AX
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MULQ 0(CX)
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ADDQ AX,R8
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ADCQ DX,R9
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MOVQ 0(SI),AX
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MULQ 8(CX)
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MOVQ AX,R10
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MOVQ DX,R11
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MOVQ 0(SI),AX
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MULQ 16(CX)
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MOVQ AX,R12
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MOVQ DX,R13
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MOVQ 0(SI),AX
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MULQ 24(CX)
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MOVQ AX,R14
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MOVQ DX,R15
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MOVQ 0(SI),AX
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MULQ 32(CX)
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MOVQ AX,BX
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MOVQ DX,BP
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MOVQ 8(SI),AX
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MULQ 0(CX)
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ADDQ AX,R10
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ADCQ DX,R11
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MOVQ 8(SI),AX
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MULQ 8(CX)
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ADDQ AX,R12
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ADCQ DX,R13
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MOVQ 8(SI),AX
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MULQ 16(CX)
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ADDQ AX,R14
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ADCQ DX,R15
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MOVQ 8(SI),AX
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MULQ 24(CX)
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ADDQ AX,BX
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ADCQ DX,BP
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MOVQ 8(SI),DX
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IMUL3Q $19,DX,AX
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MULQ 32(CX)
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ADDQ AX,R8
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ADCQ DX,R9
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MOVQ 16(SI),AX
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MULQ 0(CX)
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ADDQ AX,R12
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ADCQ DX,R13
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MOVQ 16(SI),AX
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MULQ 8(CX)
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ADDQ AX,R14
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ADCQ DX,R15
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MOVQ 16(SI),AX
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MULQ 16(CX)
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ADDQ AX,BX
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ADCQ DX,BP
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MOVQ 16(SI),DX
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IMUL3Q $19,DX,AX
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MULQ 24(CX)
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ADDQ AX,R8
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ADCQ DX,R9
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MOVQ 16(SI),DX
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IMUL3Q $19,DX,AX
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MULQ 32(CX)
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ADDQ AX,R10
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ADCQ DX,R11
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MOVQ 24(SI),AX
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MULQ 0(CX)
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ADDQ AX,R14
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ADCQ DX,R15
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MOVQ 24(SI),AX
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MULQ 8(CX)
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ADDQ AX,BX
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ADCQ DX,BP
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MOVQ 0(SP),AX
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MULQ 24(CX)
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ADDQ AX,R10
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ADCQ DX,R11
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MOVQ 0(SP),AX
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MULQ 32(CX)
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ADDQ AX,R12
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ADCQ DX,R13
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MOVQ 32(SI),AX
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MULQ 0(CX)
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ADDQ AX,BX
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ADCQ DX,BP
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MOVQ 8(SP),AX
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MULQ 16(CX)
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ADDQ AX,R10
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ADCQ DX,R11
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MOVQ 8(SP),AX
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MULQ 24(CX)
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ADDQ AX,R12
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ADCQ DX,R13
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MOVQ 8(SP),AX
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MULQ 32(CX)
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ADDQ AX,R14
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ADCQ DX,R15
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MOVQ ·REDMASK51(SB),SI
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SHLQ $13,R9:R8
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ANDQ SI,R8
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SHLQ $13,R11:R10
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ANDQ SI,R10
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ADDQ R9,R10
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SHLQ $13,R13:R12
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ANDQ SI,R12
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ADDQ R11,R12
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SHLQ $13,R15:R14
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ANDQ SI,R14
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ADDQ R13,R14
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SHLQ $13,BP:BX
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ANDQ SI,BX
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ADDQ R15,BX
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IMUL3Q $19,BP,DX
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ADDQ DX,R8
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MOVQ R8,DX
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SHRQ $51,DX
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ADDQ R10,DX
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MOVQ DX,CX
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SHRQ $51,DX
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ANDQ SI,R8
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ADDQ R12,DX
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MOVQ DX,R9
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SHRQ $51,DX
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ANDQ SI,CX
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ADDQ R14,DX
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MOVQ DX,AX
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SHRQ $51,DX
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ANDQ SI,R9
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ADDQ BX,DX
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MOVQ DX,R10
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SHRQ $51,DX
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ANDQ SI,AX
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IMUL3Q $19,DX,DX
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ADDQ DX,R8
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ANDQ SI,R10
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MOVQ R8,0(DI)
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MOVQ CX,8(DI)
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MOVQ R9,16(DI)
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MOVQ AX,24(DI)
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MOVQ R10,32(DI)
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RET
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