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212 lines
5.7 KiB
Markdown
212 lines
5.7 KiB
Markdown
# MOS Technology 6522 Versatile Interface Adapter (VIA)
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## 1. Overview
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The **MOS Technology 6522 VIA** is a general-purpose I/O controller designed to interface the 6502 family of microprocessors with external peripherals. Introduced in the mid-1970s, it provides parallel I/O ports, timers, shift register support, and interrupt handling. The 6522 is widely used in systems such as the Commodore PET, VIC-20, Apple II, BBC Micro, and many 6502-based embedded designs.
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---
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## 2. General Characteristics
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| Feature | Description |
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| -------------- | -------------------------------- |
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| Data width | 8-bit |
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| Addressing | Memory-mapped I/O |
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| Registers | 16 (4-bit register select) |
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| I/O ports | Two 8-bit ports (Port A, Port B) |
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| Timers | Two 16-bit timers |
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| Shift register | 8-bit serial I/O |
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| Interrupts | Maskable, multiple sources |
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| Clock | System clock (φ2) |
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---
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## 3. Pin Functions (Logical)
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### 3.1 Port A (PA0-PA7)
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* 8-bit bidirectional parallel I/O
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* Handshake support via CA1 / CA2
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### 3.2 Port B (PB0-PB7)
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* 8-bit bidirectional parallel I/O
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* Handshake support via CB1 / CB2
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* PB6 and PB7 may be controlled by Timer 1
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### 3.3 Control Pins
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| Pin | Description |
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| --------- | ------------------------------------- |
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| CA1 / CB1 | Interrupt-capable control inputs |
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| CA2 / CB2 | Handshake / pulse / interrupt pins |
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| IRQ | Interrupt request output (active low) |
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| RESET | Reset input |
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---
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## 4. Register Map
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Registers are selected using 4 address lines (RS0-RS3). The base address is system-defined.
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| Offset | Register | Description |
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| -----: | --------- | ------------------------------------ |
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| $0 | ORB | Output Register B |
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| $1 | ORA / IRB | Output Register A / Input Register B |
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| $2 | DDRB | Data Direction Register B |
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| $3 | DDRA | Data Direction Register A |
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| $4 | T1C-L | Timer 1 Counter Low |
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| $5 | T1C-H | Timer 1 Counter High |
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| $6 | T1L-L | Timer 1 Latch Low |
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| $7 | T1L-H | Timer 1 Latch High |
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| $8 | T2C-L | Timer 2 Counter Low |
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| $9 | T2C-H | Timer 2 Counter High |
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| $A | SR | Shift Register |
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| $B | ACR | Auxiliary Control Register |
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| $C | PCR | Peripheral Control Register |
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| $D | IFR | Interrupt Flag Register |
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| $E | IER | Interrupt Enable Register |
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| $F | ORA / IRA | Output Register A / Input Register A |
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---
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## 5. Data Direction Registers (DDRA / DDRB)
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Each bit controls the direction of its corresponding port pin:
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* `0` = Input
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* `1` = Output
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```text
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DDRB bit = 1 PBx is output
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DDRB bit = 0 PBx is input
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```
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---
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## 6. Timers
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### 6.1 Timer 1 (T1)
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* 16-bit down counter
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* Can operate in one-shot or free-running mode
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* Can toggle PB7 on timeout
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* Generates interrupts
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### 6.2 Timer 2 (T2)
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* 16-bit down counter
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* Supports pulse counting on PB6
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* One-shot operation only
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---
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## 7. Shift Register (SR)
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* 8-bit shift register
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* Can shift data in or out
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* Clock source selectable via ACR
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* Often used for serial communication or keyboard scanning
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---
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## 8. Control Registers
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### 8.1 Auxiliary Control Register (ACR)
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| Bit | Function |
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| --: | ---------------------------------- |
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| 7 | Timer 1 control (PB7 output) |
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| 6 | Timer 1 mode (free-run / one-shot) |
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| 5 | Timer 2 control |
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| 4 | Shift register mode |
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| 3 | Shift register clock source |
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| 2 | Port B latching |
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| 1 | Port A latching |
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| 0 | Unused |
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### 8.2 Peripheral Control Register (PCR)
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Controls CA1, CA2, CB1, CB2 behavior:
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* Input/output mode
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* Active edge selection
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* Pulse or handshake modes
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---
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## 9. Interrupt System
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### 9.1 Interrupt Flag Register (IFR)
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| Bit | Source |
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| --: | ---------------------------------- |
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| 7 | IRQ status (any enabled interrupt) |
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| 6 | Timer 1 |
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| 5 | Timer 2 |
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| 4 | CB1 |
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| 3 | CB2 |
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| 2 | Shift Register |
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| 1 | CA1 |
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| 0 | CA2 |
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### 9.2 Interrupt Enable Register (IER)
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* Bit 7 determines set/clear mode:
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* `1` = set bits
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* `0` = clear bits
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```text
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Write $80 | mask enable interrupts
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Write $00 | mask disable interrupts
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```
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---
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## 10. Reset Behavior
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On RESET:
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* All DDR bits cleared (ports default to input)
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* Timers stopped
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* Shift register disabled
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* Interrupts disabled
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---
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## 11. Timing Notes
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* VIA registers are accessed synchronously with φ2
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* Timer counters decrement once per φ2 cycle
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* Some operations have side effects when reading/writing registers
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---
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## 12. Common Use Cases
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* Keyboard and joystick interfaces
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* Parallel printer interfaces
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* Timers and event counting
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* Simple serial communications
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* General-purpose GPIO expansion
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---
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## 13. Variants and Related Chips
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| Chip | Notes |
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| ----- | ----------------------------- |
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| 6522 | Original NMOS VIA |
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| 65C22 | CMOS VIA, faster, lower power |
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| 6520 | Earlier PIA (simpler) |
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---
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## 14. References
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* <https://en.wikipedia.org/wiki/MOS_Technology_6522>
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* <https://grokipedia.com/page/MOS_Technology_6522>
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---
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