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246 lines
5.1 KiB
Markdown
246 lines
5.1 KiB
Markdown
# AT28C256 EEPROM Emulation Specification
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## Overview
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This document specifies how to **emulate the AT28C256 (32 KB Parallel EEPROM)** in a 6502-based system emulator. The goal is *behavioral accuracy* suitable for SBCs, monitors, and real ROM images, not just generic file-backed storage.
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The AT28C256 is commonly used as **ROM** in 6502 systems, but it is *electrically writable* and has timing behaviors that differ from SRAM.
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---
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## Chip Summary
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| Parameter | Value |
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| -------------- | ---------------------- |
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| Capacity | 32 KB (256 Kbit) |
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| Organization | 32,768 x 8 |
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| Address Lines | A0-A14 |
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| Data Lines | D0-D7 |
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| Supply Voltage | 5V |
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| Typical Use | ROM / Firmware storage |
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## Pin Definitions
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| Pin | Name | Function |
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| ------ | ------------- | ---------------------- |
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| A0-A14 | Address | Byte address |
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| D0-D7 | Data | Data bus |
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| /CE | Chip Enable | Activates chip |
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| /OE | Output Enable | Enables output drivers |
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| /WE | Write Enable | Triggers write cycle |
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| VCC | +5V | Power |
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| GND | Ground | Reference |
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---
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## Read Cycle Behavior
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A read occurs when:
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```
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/CE = 0
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/OE = 0
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/WE = 1
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```
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### Read Rules
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* Address must be stable before `/OE` is asserted
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* Data appears on D0-D7 after access time (ignored in most emulators)
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* Output is **high-impedance** when `/OE = 1` or `/CE = 1`
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### Emulator Behavior
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```text
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if CE == 0 and OE == 0 and WE == 1:
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data_bus = memory[address]
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else:
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data_bus = Z
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```
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---
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## Write Cycle Behavior
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A write occurs when:
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```
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/CE = 0
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/WE = 0
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```
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(`/OE` is typically HIGH during writes)
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### Important EEPROM Characteristics
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* Writes are **not instantaneous**
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* Each write triggers an **internal programming cycle**
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* During programming, reads may return undefined data
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---
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## Write Timing Model (Simplified)
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### Real Hardware
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| Parameter | Typical |
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| --------------- | -------- |
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| Byte Write Time | ~200 µs |
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| Page Size | 64 bytes |
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| Page Write Time | ~10 ms |
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### Emulator Simplification Options
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#### Option A - Instant Writes (Common)
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* Write immediately updates memory
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* No busy state
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* Recommended for early emulators
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#### Option B - Cycle-Based Busy State (Advanced)
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* Track a "write in progress" timer
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* Reads during write return last value or `0xFF`
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* Writes ignored until cycle completes
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---
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## Page Write Emulation (Optional)
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* Page size: **64 bytes**
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* Writes within same page before timeout commit together
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* Crossing page boundary wraps within page (hardware quirk)
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Simplified rule:
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```text
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page_base = address & 0xFFC0
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page_offset = address & 0x003F
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```
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---
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## Write Protection Behavior
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Some systems treat EEPROM as **ROM-only** after programming.
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Emulator may support:
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* Read-only mode (writes ignored)
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* Programmable mode (writes allowed)
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* Runtime toggle (simulates programming jumper)
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---
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## Power-Up State
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* EEPROM retains contents
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* No undefined data on power-up
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Emulator should:
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* Load contents from image file
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* Preserve data across resets
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---
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## Bus Contention Rules
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| Condition | Behavior |
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| ------------------- | ----------------- |
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| /CE = 1 | Data bus = Z |
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| /OE = 1 | Data bus = Z |
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| /WE = 0 and /OE = 0 | Undefined (avoid) |
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Emulator may:
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* Prioritize write
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* Or flag invalid state
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---
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## Memory Mapping in 6502 Systems
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Common layout:
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```
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$0000-$7FFF RAM
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$8000-$FFFF AT28C256 EEPROM
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```
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### Reset Vector Usage
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| Vector | Address |
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| ------ | ----------- |
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| RESET | $FFFC-$FFFD |
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| NMI | $FFFA-$FFFB |
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| IRQ | $FFFE-$FFFF |
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---
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## Emulator API Model
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```c
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typedef struct {
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uint8_t memory[32768];
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bool write_enabled;
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bool busy;
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uint32_t busy_cycles;
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} AT28C256;
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```
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### Read
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```c
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uint8_t eeprom_read(addr);
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```
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### Write
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```c
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void eeprom_write(addr, value);
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```
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---
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## Recommended Emulator Defaults
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| Feature | Setting |
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| ------------- | ----------- |
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| Write Delay | Disabled |
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| Page Mode | Disabled |
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| Write Protect | Enabled |
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| Persistence | File-backed |
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---
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## Testing Checklist
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* Reset vector fetch
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* ROM reads under normal execution
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* Writes ignored in read-only mode
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* Correct address masking (15 bits)
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* No bus drive when disabled
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## References
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* [AT28C256 Datasheet (Microchip)](https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/AT28C256-Industrial-Grade-256-Kbit-Paged-Parallel-EEPROM-Data-Sheet-DS20006386.pdf)
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* [Ben Eater 6502 Computer Series](https://eater.net/6502)
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* <https://www.youtube.com/watch?v=oO8_2JJV0B4>
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* [6502.org Memory Mapping Notes](https://6502.co.uk/lesson/memory-map)
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---
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## Notes
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This specification intentionally mirrors **real hardware quirks** while allowing emulator authors to choose between simplicity and accuracy. It is suitable for:
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* Educational emulators
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* SBC simulation
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* ROM development workflows
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* Integration with 6502 + 6522 + SRAM emulation
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