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add reference files for new skill legacy-circuit-mockups
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skills/legacy-circuit-mockups/references/emulator-6522.md
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skills/legacy-circuit-mockups/references/emulator-6522.md
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# 6522 VIA (Versatile Interface Adapter) Emulation Specification
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A technical Markdown specification for **emulating the MOS Technology / WDC 6522 VIA**, suitable for 6502-family emulators, SBC simulators, and retrocomputing software environments.
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---
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## 1. Scope
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This document defines the functional behavior required to emulate:
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* MOS Technology 6522 VIA
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* WDC 65C22 VIA (CMOS variant, where noted)
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Out of scope:
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* Analog electrical characteristics
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* Bus contention and propagation delay
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* Undocumented silicon race conditions
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---
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## 2. Chip Overview
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### Core Features
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| Feature | Description |
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| ---------------- | ------------------------------------ |
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| I/O Ports | Two 8-bit bidirectional ports (A, B) |
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| Timers | Two programmable timers |
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| Shift Register | 8-bit serial shift register |
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| Interrupt System | Maskable, prioritized |
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| Handshaking | CA1/CA2, CB1/CB2 control lines |
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---
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## 3. External Signals (Logical Model)
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| Signal | Direction | Purpose |
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| -------- | --------- | ------------------------ |
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| PA0-PA7 | I/O | Port A |
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| PB0-PB7 | I/O | Port B |
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| CA1, CA2 | I/O | Control lines A |
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| CB1, CB2 | I/O | Control lines B |
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| IRQ | Output | Interrupt request to CPU |
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| CS1, CS2 | Input | Chip select |
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| R/W | Input | Read / write |
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| RS0-RS3 | Input | Register select |
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---
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## 4. Register Map
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Registers are selected using RS3-RS0.
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| Address | Name | R/W | Description |
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| ------- | ----------- | --- | -------------------------------- |
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| 0 | ORB / IRB | R/W | Output/Input Register B |
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| 1 | ORA / IRA | R/W | Output/Input Register A |
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| 2 | DDRB | R/W | Data Direction Register B |
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| 3 | DDRA | R/W | Data Direction Register A |
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| 4 | T1C-L | R | Timer 1 Counter Low |
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| 5 | T1C-H | R | Timer 1 Counter High |
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| 6 | T1L-L | W | Timer 1 Latch Low |
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| 7 | T1L-H | W | Timer 1 Latch High |
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| 8 | T2C-L | R | Timer 2 Counter Low |
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| 9 | T2C-H | R | Timer 2 Counter High |
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| 10 | SR | R/W | Shift Register |
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| 11 | ACR | R/W | Auxiliary Control Register |
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| 12 | PCR | R/W | Peripheral Control Register |
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| 13 | IFR | R/W | Interrupt Flag Register |
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| 14 | IER | R/W | Interrupt Enable Register |
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| 15 | ORA (no HS) | R/W | Output Register A (no handshake) |
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---
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## 5. Data Direction Registers
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* Bit = 1 Output
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* Bit = 0 Input
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```text
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output = ORx & DDRx
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input = external & ~DDRx
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```
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---
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## 6. Port Behavior
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### Read
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* Returns input pins for bits configured as input
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* Returns output latch for bits configured as output
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### Write
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* Updates output latch only
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* Actual pin value depends on DDR
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---
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## 7. Timers
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### Timer 1 (T1)
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* 16-bit down counter
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* Can generate interrupts
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* Optional PB7 toggle
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### Timer 2 (T2)
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* 16-bit down counter
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* One-shot or pulse counting (CB1)
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### Timer Emulation Rules
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* Decrement once per CPU cycle
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* Reload from latch when appropriate
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* Set interrupt flag on underflow
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---
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## 8. Shift Register (SR)
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Modes controlled via ACR:
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* Disabled
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* Shift in under CB1 clock
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* Shift out under system clock
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Emulator requirements:
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* 8-bit shift
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* Correct bit order
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* Optional external clock handling
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---
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## 9. Control Registers
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### Auxiliary Control Register (ACR)
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Controls:
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* Timer 1 mode
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* Timer 2 mode
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* Shift register mode
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* PB7 behavior
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### Peripheral Control Register (PCR)
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Controls:
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* CA1/CB1 edge sensitivity
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* CA2/CB2 handshake / pulse / output modes
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---
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## 10. Interrupt System
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### Interrupt Flag Register (IFR)
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| Bit | Source |
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| --- | -------------------------- |
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| 0 | CA2 |
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| 1 | CA1 |
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| 2 | Shift Register |
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| 3 | CB2 |
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| 4 | CB1 |
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| 5 | Timer 2 |
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| 6 | Timer 1 |
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| 7 | Any interrupt (logical OR) |
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### Interrupt Enable Register (IER)
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* Bit 7 = set/clear mode
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* Bits 0-6 enable individual sources
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### IRQ Logic
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```text
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IRQ = (IFR & IER & 0x7F) != 0
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```
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---
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## 11. Handshaking Lines
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### CA1 / CB1
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* Edge-detect inputs
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* Trigger interrupts
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### CA2 / CB2
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* Input or output
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* Pulse or handshake modes
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Emulator must:
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* Track pin state
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* Detect configured edges
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---
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## 12. Reset Behavior
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On reset:
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* DDRx = $00
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* ORx = $00
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* Timers stopped
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* IFR cleared
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* IER cleared
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* IRQ inactive
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---
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## 13. Read/Write Side Effects
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| Register | Side Effect |
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| ----------- | ------------------------ |
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| ORA/ORB | Clears handshake flags |
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| T1C-H write | Loads and starts Timer 1 |
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| IFR write | Clears written bits |
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| IER write | Sets or clears enables |
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---
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## 14. Emulation Timing Levels
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| Level | Description |
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| -------------- | ------------------------- |
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| Functional | Correct register behavior |
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| Cycle-based | Timers tick per CPU cycle |
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| Cycle-accurate | Matches real VIA timing |
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---
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## 15. Integration with 6502 Emulator
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```text
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CPU cycle VIA tick update timers update IRQ
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```
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* VIA must be clocked in sync with CPU
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* IRQ line sampled by CPU at instruction boundaries
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---
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## 16. Testing and Validation
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### Recommended Tests
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* VIA timer test ROMs
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* Port read/write tests
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* Interrupt priority tests
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### Validation Checklist
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* Timers count correctly
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* IRQ asserts and clears properly
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* DDR behavior correct
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* Side effects implemented
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---
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## 17. Differences: 6522 vs 65C22 (Summary)
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| Feature | 6522 | 65C22 |
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| -------------- | ------ | -------- |
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| Power | Higher | Lower |
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| Decimal quirks | N/A | Fixed |
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| Timer accuracy | NMOS | Improved |
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---
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## 18. Reference Links
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* [https://www.westerndesigncenter.com/wdc/documentation](https://www.westerndesigncenter.com/wdc/documentation)
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* [https://www.princeton.edu/~mae412/HANDOUTS/Datasheets/6522.pdf](https://www.princeton.edu/~mae412/HANDOUTS/Datasheets/6522.pdf)
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* [https://www.nesdev.org/wiki/6522](https://www.nesdev.org/wiki/6522)
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---
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**Document Scope:** Software emulation of the 6522 VIA
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**Audience:** Emulator developers, SBC designers
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**Status:** Stable technical reference
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