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Merge branch 'main' into jamont-skill-imagemagick
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216
skills/azure-deployment-preflight/SKILL.md
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216
skills/azure-deployment-preflight/SKILL.md
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---
|
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name: azure-deployment-preflight
|
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description: 'Performs comprehensive preflight validation of Bicep deployments to Azure, including template syntax validation, what-if analysis, and permission checks. Use this skill before any deployment to Azure to preview changes, identify potential issues, and ensure the deployment will succeed. Activate when users mention deploying to Azure, validating Bicep files, checking deployment permissions, previewing infrastructure changes, running what-if, or preparing for azd provision.'
|
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---
|
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|
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# Azure Deployment Preflight Validation
|
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|
||||
This skill validates Bicep deployments before execution, supporting both Azure CLI (`az`) and Azure Developer CLI (`azd`) workflows.
|
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|
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## When to Use This Skill
|
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|
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- Before deploying infrastructure to Azure
|
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- When preparing or reviewing Bicep files
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- To preview what changes a deployment will make
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- To verify permissions are sufficient for deployment
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- Before running `azd up`, `azd provision`, or `az deployment` commands
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|
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## Validation Process
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Follow these steps in order. Continue to the next step even if a previous step fails—capture all issues in the final report.
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### Step 1: Detect Project Type
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Determine the deployment workflow by checking for project indicators:
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|
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1. **Check for azd project**: Look for `azure.yaml` in the project root
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- If found → Use **azd workflow**
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- If not found → Use **az CLI workflow**
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2. **Locate Bicep files**: Find all `.bicep` files to validate
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- For azd projects: Check `infra/` directory first, then project root
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- For standalone: Use the file specified by the user or search common locations (`infra/`, `deploy/`, project root)
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3. **Auto-detect parameter files**: For each Bicep file, look for matching parameter files:
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- `<filename>.bicepparam` (Bicep parameters - preferred)
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- `<filename>.parameters.json` (JSON parameters)
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- `parameters.json` or `parameters/<env>.json` in same directory
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### Step 2: Validate Bicep Syntax
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Run Bicep CLI to check template syntax before attempting deployment validation:
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|
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```bash
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bicep build <bicep-file> --stdout
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```
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|
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**What to capture:**
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- Syntax errors with line/column numbers
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- Warning messages
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- Build success/failure status
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**If Bicep CLI is not installed:**
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- Note the issue in the report
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- Continue to Step 3 (Azure will validate syntax during what-if)
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### Step 3: Run Preflight Validation
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Choose the appropriate validation based on project type detected in Step 1.
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#### For azd Projects (azure.yaml exists)
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Use `azd provision --preview` to validate the deployment:
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```bash
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azd provision --preview
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```
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|
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If an environment is specified or multiple environments exist:
|
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```bash
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azd provision --preview --environment <env-name>
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```
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#### For Standalone Bicep (no azure.yaml)
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Determine the deployment scope from the Bicep file's `targetScope` declaration:
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| Target Scope | Command |
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||||
|--------------|---------|
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| `resourceGroup` (default) | `az deployment group what-if` |
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| `subscription` | `az deployment sub what-if` |
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| `managementGroup` | `az deployment mg what-if` |
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| `tenant` | `az deployment tenant what-if` |
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**Run with Provider validation level first:**
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```bash
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# Resource Group scope (most common)
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az deployment group what-if \
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--resource-group <rg-name> \
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--template-file <bicep-file> \
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--parameters <param-file> \
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--validation-level Provider
|
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|
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# Subscription scope
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az deployment sub what-if \
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--location <location> \
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--template-file <bicep-file> \
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--parameters <param-file> \
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--validation-level Provider
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||||
|
||||
# Management Group scope
|
||||
az deployment mg what-if \
|
||||
--location <location> \
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||||
--management-group-id <mg-id> \
|
||||
--template-file <bicep-file> \
|
||||
--parameters <param-file> \
|
||||
--validation-level Provider
|
||||
|
||||
# Tenant scope
|
||||
az deployment tenant what-if \
|
||||
--location <location> \
|
||||
--template-file <bicep-file> \
|
||||
--parameters <param-file> \
|
||||
--validation-level Provider
|
||||
```
|
||||
|
||||
**Fallback Strategy:**
|
||||
|
||||
If `--validation-level Provider` fails with permission errors (RBAC), retry with `ProviderNoRbac`:
|
||||
|
||||
```bash
|
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az deployment group what-if \
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--resource-group <rg-name> \
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||||
--template-file <bicep-file> \
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||||
--validation-level ProviderNoRbac
|
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```
|
||||
|
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Note the fallback in the report—the user may lack full deployment permissions.
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|
||||
### Step 4: Capture What-If Results
|
||||
|
||||
Parse the what-if output to categorize resource changes:
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||||
|
||||
| Change Type | Symbol | Meaning |
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||||
|-------------|--------|---------|
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||||
| Create | `+` | New resource will be created |
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||||
| Delete | `-` | Resource will be deleted |
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| Modify | `~` | Resource properties will change |
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| NoChange | `=` | Resource unchanged |
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| Ignore | `*` | Resource not analyzed (limits reached) |
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| Deploy | `!` | Resource will be deployed (changes unknown) |
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For modified resources, capture the specific property changes.
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|
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### Step 5: Generate Report
|
||||
|
||||
Create a Markdown report file in the **project root** named:
|
||||
- `preflight-report.md`
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||||
|
||||
Use the template structure from [references/REPORT-TEMPLATE.md](references/REPORT-TEMPLATE.md).
|
||||
|
||||
**Report sections:**
|
||||
1. **Summary** - Overall status, timestamp, files validated, target scope
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2. **Tools Executed** - Commands run, versions, validation levels used
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3. **Issues** - All errors and warnings with severity and remediation
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4. **What-If Results** - Resources to create/modify/delete/unchanged
|
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5. **Recommendations** - Actionable next steps
|
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|
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## Required Information
|
||||
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Before running validation, gather:
|
||||
|
||||
| Information | Required For | How to Obtain |
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|-------------|--------------|---------------|
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| Resource Group | `az deployment group` | Ask user or check existing `.azure/` config |
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| Subscription | All deployments | `az account show` or ask user |
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| Location | Sub/MG/Tenant scope | Ask user or use default from config |
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| Environment | azd projects | `azd env list` or ask user |
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If required information is missing, prompt the user before proceeding.
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||||
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||||
## Error Handling
|
||||
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||||
See [references/ERROR-HANDLING.md](references/ERROR-HANDLING.md) for detailed error handling guidance.
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||||
|
||||
**Key principle:** Continue validation even when errors occur. Capture all issues in the final report.
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||||
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||||
| Error Type | Action |
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||||
|------------|--------|
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| Not logged in | Note in report, suggest `az login` or `azd auth login` |
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| Permission denied | Fall back to `ProviderNoRbac`, note in report |
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| Bicep syntax error | Include all errors, continue to other files |
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| Tool not installed | Note in report, skip that validation step |
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| Resource group not found | Note in report, suggest creating it |
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## Tool Requirements
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This skill uses the following tools:
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||||
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||||
- **Azure CLI** (`az`) - Version 2.76.0+ recommended for `--validation-level`
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- **Azure Developer CLI** (`azd`) - For projects with `azure.yaml`
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- **Bicep CLI** (`bicep`) - For syntax validation
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||||
- **Azure MCP Tools** - For documentation lookups and best practices
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Check tool availability before starting:
|
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```bash
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az --version
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azd version
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bicep --version
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||||
```
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||||
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||||
## Example Workflow
|
||||
|
||||
1. User: "Validate my Bicep deployment before I run it"
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||||
2. Agent detects `azure.yaml` → azd project
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3. Agent finds `infra/main.bicep` and `infra/main.bicepparam`
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||||
4. Agent runs `bicep build infra/main.bicep --stdout`
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||||
5. Agent runs `azd provision --preview`
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||||
6. Agent generates `preflight-report.md` in project root
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||||
7. Agent summarizes findings to user
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## Reference Documentation
|
||||
|
||||
- [Validation Commands Reference](references/VALIDATION-COMMANDS.md)
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||||
- [Report Template](references/REPORT-TEMPLATE.md)
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||||
- [Error Handling Guide](references/ERROR-HANDLING.md)
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392
skills/azure-deployment-preflight/references/ERROR-HANDLING.md
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392
skills/azure-deployment-preflight/references/ERROR-HANDLING.md
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@@ -0,0 +1,392 @@
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# Error Handling Guide
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This reference documents common errors during preflight validation and how to handle them.
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||||
## Core Principle
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||||
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||||
**Continue on failure.** Capture all issues in the final report rather than stopping at the first error. This gives users a complete picture of what needs to be fixed.
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||||
|
||||
---
|
||||
|
||||
## Authentication Errors
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||||
|
||||
### Not Logged In (Azure CLI)
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||||
|
||||
**Detection:**
|
||||
```
|
||||
ERROR: Please run 'az login' to setup account.
|
||||
ERROR: AADSTS700082: The refresh token has expired
|
||||
```
|
||||
|
||||
**Exit Codes:** Non-zero
|
||||
|
||||
**Handling:**
|
||||
1. Note the error in the report
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||||
2. Include remediation steps
|
||||
3. Skip remaining Azure CLI commands
|
||||
4. Continue with other validation steps if possible
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
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||||
#### ❌ Azure CLI Authentication Required
|
||||
|
||||
- **Severity:** Error
|
||||
- **Source:** az cli
|
||||
- **Message:** Not logged in to Azure CLI
|
||||
- **Remediation:** Run `az login` to authenticate, then re-run preflight validation
|
||||
- **Documentation:** https://learn.microsoft.com/en-us/cli/azure/authenticate-azure-cli
|
||||
```
|
||||
|
||||
### Not Logged In (azd)
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
ERROR: not logged in, run `azd auth login` to login
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note the error in the report
|
||||
2. Skip azd commands
|
||||
3. Suggest `azd auth login`
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ❌ Azure Developer CLI Authentication Required
|
||||
|
||||
- **Severity:** Error
|
||||
- **Source:** azd
|
||||
- **Message:** Not logged in to Azure Developer CLI
|
||||
- **Remediation:** Run `azd auth login` to authenticate, then re-run preflight validation
|
||||
```
|
||||
|
||||
### Token Expired
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
AADSTS700024: Client assertion is not within its valid time range
|
||||
AADSTS50173: The provided grant has expired
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note the error
|
||||
2. Suggest re-authentication
|
||||
3. Skip Azure operations
|
||||
|
||||
---
|
||||
|
||||
## Permission Errors
|
||||
|
||||
### Insufficient RBAC Permissions
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
AuthorizationFailed: The client '...' with object id '...' does not have authorization
|
||||
to perform action '...' over scope '...'
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. **First attempt:** Retry with `--validation-level ProviderNoRbac`
|
||||
2. Note the permission limitation in the report
|
||||
3. If ProviderNoRbac also fails, report the specific missing permission
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ⚠️ Limited Permission Validation
|
||||
|
||||
- **Severity:** Warning
|
||||
- **Source:** what-if
|
||||
- **Message:** Full RBAC validation failed; using read-only validation
|
||||
- **Detail:** Missing permission: `Microsoft.Resources/deployments/write` on scope `/subscriptions/xxx`
|
||||
- **Recommendation:** Request Contributor role on the target resource group, or verify deployment permissions with your administrator
|
||||
```
|
||||
|
||||
### Resource Group Not Found
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
ResourceGroupNotFound: Resource group 'xxx' could not be found.
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note in report
|
||||
2. Suggest creating the resource group
|
||||
3. Skip what-if for this scope
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ❌ Resource Group Does Not Exist
|
||||
|
||||
- **Severity:** Error
|
||||
- **Source:** what-if
|
||||
- **Message:** Resource group 'my-rg' does not exist
|
||||
- **Remediation:** Create the resource group before deployment:
|
||||
```bash
|
||||
az group create --name my-rg --location eastus
|
||||
```
|
||||
```
|
||||
|
||||
### Subscription Access Denied
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
SubscriptionNotFound: The subscription 'xxx' could not be found.
|
||||
InvalidSubscriptionId: Subscription '...' is not valid
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note in report
|
||||
2. Suggest checking subscription ID
|
||||
3. List available subscriptions
|
||||
|
||||
---
|
||||
|
||||
## Bicep Syntax Errors
|
||||
|
||||
### Compilation Errors
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
/path/main.bicep(22,51) : Error BCP064: Found unexpected tokens
|
||||
/path/main.bicep(10,5) : Error BCP018: Expected the "=" character at this location
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Parse error output for line/column numbers
|
||||
2. Include all errors in report (don't stop at first)
|
||||
3. Continue to what-if (may provide additional context)
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ❌ Bicep Syntax Error
|
||||
|
||||
- **Severity:** Error
|
||||
- **Source:** bicep build
|
||||
- **Location:** `main.bicep:22:51`
|
||||
- **Code:** BCP064
|
||||
- **Message:** Found unexpected tokens in interpolated expression
|
||||
- **Remediation:** Check the string interpolation syntax at line 22
|
||||
- **Documentation:** https://learn.microsoft.com/en-us/azure/azure-resource-manager/bicep/diagnostics/bcp064
|
||||
```
|
||||
|
||||
### Module Not Found
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
Error BCP091: An error occurred reading file. Could not find file '...'
|
||||
Error BCP190: The module is not valid
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note missing module
|
||||
2. Check if `bicep restore` is needed
|
||||
3. Verify module path
|
||||
|
||||
### Parameter File Issues
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
Error BCP032: The value must be a compile-time constant
|
||||
Error BCP035: The specified object is missing required properties
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note parameter issues
|
||||
2. Indicate which parameters are problematic
|
||||
3. Suggest fixes
|
||||
|
||||
---
|
||||
|
||||
## Tool Not Installed
|
||||
|
||||
### Azure CLI Not Found
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
'az' is not recognized as an internal or external command
|
||||
az: command not found
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note in report
|
||||
2. Provide installation instructions.
|
||||
- If available use the Azure MCP `extension_cli_install` tool to get installation instructions.
|
||||
- Otherwise look for instructions at https://learn.microsoft.com/en-us/cli/azure/install-azure-cli.
|
||||
3. Skip az commands
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ⏭️ Azure CLI Not Installed
|
||||
|
||||
- **Severity:** Warning
|
||||
- **Source:** environment
|
||||
- **Message:** Azure CLI (az) is not installed or not in PATH
|
||||
- **Remediation:** Install the Azure CLI <ADD INSTALLATION INSTRUCTIONS HERE>
|
||||
- **Impact:** What-if validation using az commands was skipped
|
||||
```
|
||||
|
||||
### Bicep CLI Not Found
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
'bicep' is not recognized as an internal or external command
|
||||
bicep: command not found
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note in report
|
||||
2. Azure CLI may have built-in Bicep - try `az bicep build`
|
||||
3. Provide installation link
|
||||
|
||||
**Report Entry:**
|
||||
```markdown
|
||||
#### ⏭️ Bicep CLI Not Installed
|
||||
|
||||
- **Severity:** Warning
|
||||
- **Source:** environment
|
||||
- **Message:** Bicep CLI is not installed
|
||||
- **Remediation:** Install Bicep CLI: https://learn.microsoft.com/en-us/azure/azure-resource-manager/bicep/install
|
||||
- **Impact:** Syntax validation was skipped; Azure will validate during what-if
|
||||
```
|
||||
|
||||
### Azure Developer CLI Not Found
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
'azd' is not recognized as an internal or external command
|
||||
azd: command not found
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. If `azure.yaml` exists, this is required
|
||||
2. Fall back to az CLI commands if possible
|
||||
3. Note in report
|
||||
|
||||
---
|
||||
|
||||
## What-If Specific Errors
|
||||
|
||||
### Nested Template Limits
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
The deployment exceeded the nested template limit of 500
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note as warning (not error)
|
||||
2. Explain affected resources show as "Ignore"
|
||||
3. Suggest manual review
|
||||
|
||||
### Template Link Not Supported
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
templateLink references in nested deployments won't be visible in what-if
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note as warning
|
||||
2. Explain limitation
|
||||
3. Resources will be verified during actual deployment
|
||||
|
||||
### Unevaluated Expressions
|
||||
|
||||
**Detection:** Properties showing function names like `[utcNow()]` instead of values
|
||||
|
||||
**Handling:**
|
||||
1. Note as informational
|
||||
2. Explain these are evaluated at deployment time
|
||||
3. Not an error
|
||||
|
||||
---
|
||||
|
||||
## Network Errors
|
||||
|
||||
### Timeout
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
Connection timed out
|
||||
Request timed out
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Suggest retry
|
||||
2. Check network connectivity
|
||||
3. May indicate Azure service issues
|
||||
|
||||
### SSL/TLS Errors
|
||||
|
||||
**Detection:**
|
||||
```
|
||||
SSL: CERTIFICATE_VERIFY_FAILED
|
||||
unable to get local issuer certificate
|
||||
```
|
||||
|
||||
**Handling:**
|
||||
1. Note in report
|
||||
2. May indicate proxy or corporate firewall
|
||||
3. Suggest checking SSL settings
|
||||
|
||||
---
|
||||
|
||||
## Fallback Strategy
|
||||
|
||||
When primary validation fails, attempt fallbacks in order:
|
||||
|
||||
```
|
||||
Provider (full RBAC validation)
|
||||
↓ fails with permission error
|
||||
ProviderNoRbac (validation without write permission check)
|
||||
↓ fails
|
||||
Template (static syntax only)
|
||||
↓ fails
|
||||
Report all failures and skip what-if analysis
|
||||
```
|
||||
|
||||
**Always continue to generate the report**, even if all validation steps fail.
|
||||
|
||||
---
|
||||
|
||||
## Error Report Aggregation
|
||||
|
||||
When multiple errors occur, aggregate them logically:
|
||||
|
||||
1. **Group by source** (bicep, what-if, permissions)
|
||||
2. **Order by severity** (errors before warnings)
|
||||
3. **Deduplicate** similar errors
|
||||
4. **Provide summary count** at the top
|
||||
|
||||
Example:
|
||||
```markdown
|
||||
## Issues
|
||||
|
||||
Found **3 errors** and **2 warnings**
|
||||
|
||||
### Errors (3)
|
||||
|
||||
1. [Bicep Syntax Error - main.bicep:22:51](#error-1)
|
||||
2. [Bicep Syntax Error - main.bicep:45:10](#error-2)
|
||||
3. [Resource Group Not Found](#error-3)
|
||||
|
||||
### Warnings (2)
|
||||
|
||||
1. [Limited Permission Validation](#warning-1)
|
||||
2. [Nested Template Limit Reached](#warning-2)
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Exit Code Reference
|
||||
|
||||
| Tool | Exit Code | Meaning |
|
||||
|------|-----------|---------|
|
||||
| az | 0 | Success |
|
||||
| az | 1 | General error |
|
||||
| az | 2 | Command not found |
|
||||
| az | 3 | Required argument missing |
|
||||
| azd | 0 | Success |
|
||||
| azd | 1 | Error |
|
||||
| bicep | 0 | Build succeeded |
|
||||
| bicep | 1 | Build failed (errors) |
|
||||
| bicep | 2 | Build succeeded with warnings |
|
||||
352
skills/azure-deployment-preflight/references/REPORT-TEMPLATE.md
Normal file
352
skills/azure-deployment-preflight/references/REPORT-TEMPLATE.md
Normal file
@@ -0,0 +1,352 @@
|
||||
# Preflight Report Template
|
||||
|
||||
Use this template structure when generating `preflight-report.md` in the project root.
|
||||
|
||||
---
|
||||
|
||||
## Template
|
||||
|
||||
```markdown
|
||||
# Azure Deployment Preflight Report
|
||||
|
||||
**Generated:** {timestamp}
|
||||
**Status:** {overall-status}
|
||||
|
||||
---
|
||||
|
||||
## Summary
|
||||
|
||||
| Property | Value |
|
||||
|----------|-------|
|
||||
| **Template File(s)** | {bicep-files} |
|
||||
| **Parameter File(s)** | {param-files-or-none} |
|
||||
| **Project Type** | {azd-project | standalone-bicep} |
|
||||
| **Deployment Scope** | {resourceGroup | subscription | managementGroup | tenant} |
|
||||
| **Target** | {resource-group-name | subscription-name | mg-id} |
|
||||
| **Validation Level** | {Provider | ProviderNoRbac} |
|
||||
|
||||
### Validation Results
|
||||
|
||||
| Check | Status | Details |
|
||||
|-------|--------|---------|
|
||||
| Bicep Syntax | {✅ Pass | ❌ Fail | ⚠️ Warnings | ⏭️ Skipped} | {details} |
|
||||
| What-If Analysis | {✅ Pass | ❌ Fail | ⏭️ Skipped} | {details} |
|
||||
| Permission Check | {✅ Pass | ⚠️ Limited | ❌ Fail} | {details} |
|
||||
|
||||
---
|
||||
|
||||
## Tools Executed
|
||||
|
||||
### Commands Run
|
||||
|
||||
| Step | Command | Exit Code | Duration |
|
||||
|------|---------|-----------|----------|
|
||||
| 1 | `{command}` | {0 | non-zero} | {duration} |
|
||||
| 2 | `{command}` | {0 | non-zero} | {duration} |
|
||||
|
||||
### Tool Versions
|
||||
|
||||
| Tool | Version |
|
||||
|------|---------|
|
||||
| Azure CLI | {version} |
|
||||
| Bicep CLI | {version} |
|
||||
| Azure Developer CLI | {version-or-n/a} |
|
||||
|
||||
---
|
||||
|
||||
## Issues
|
||||
|
||||
{if-no-issues}
|
||||
✅ **No issues found.** The deployment is ready to proceed.
|
||||
{end-if}
|
||||
|
||||
{if-issues-exist}
|
||||
### Errors
|
||||
|
||||
{for-each-error}
|
||||
#### ❌ {error-title}
|
||||
|
||||
- **Severity:** Error
|
||||
- **Source:** {bicep-build | what-if | permissions}
|
||||
- **Location:** {file-path}:{line}:{column} (if applicable)
|
||||
- **Message:** {error-message}
|
||||
- **Remediation:** {suggested-fix}
|
||||
- **Documentation:** {link-if-available}
|
||||
|
||||
{end-for-each}
|
||||
|
||||
### Warnings
|
||||
|
||||
{for-each-warning}
|
||||
#### ⚠️ {warning-title}
|
||||
|
||||
- **Severity:** Warning
|
||||
- **Source:** {source}
|
||||
- **Message:** {warning-message}
|
||||
- **Recommendation:** {suggested-action}
|
||||
|
||||
{end-for-each}
|
||||
{end-if}
|
||||
|
||||
---
|
||||
|
||||
## What-If Results
|
||||
|
||||
{if-what-if-succeeded}
|
||||
|
||||
### Change Summary
|
||||
|
||||
| Change Type | Count |
|
||||
|-------------|-------|
|
||||
| 🆕 Create | {count} |
|
||||
| 📝 Modify | {count} |
|
||||
| 🗑️ Delete | {count} |
|
||||
| ✓ No Change | {count} |
|
||||
| ⚠️ Ignore | {count} |
|
||||
|
||||
### Resources to Create
|
||||
|
||||
{if-resources-to-create}
|
||||
| Resource Type | Resource Name |
|
||||
|---------------|---------------|
|
||||
| {type} | {name} |
|
||||
{end-if}
|
||||
|
||||
{if-no-resources-to-create}
|
||||
*No resources will be created.*
|
||||
{end-if}
|
||||
|
||||
### Resources to Modify
|
||||
|
||||
{if-resources-to-modify}
|
||||
#### {resource-type}/{resource-name}
|
||||
|
||||
| Property | Current Value | New Value |
|
||||
|----------|---------------|-----------|
|
||||
| {property-path} | {current} | {new} |
|
||||
|
||||
{end-if}
|
||||
|
||||
{if-no-resources-to-modify}
|
||||
*No resources will be modified.*
|
||||
{end-if}
|
||||
|
||||
### Resources to Delete
|
||||
|
||||
{if-resources-to-delete}
|
||||
| Resource Type | Resource Name |
|
||||
|---------------|---------------|
|
||||
| {type} | {name} |
|
||||
|
||||
> ⚠️ **Warning:** Resources listed for deletion will be permanently removed.
|
||||
{end-if}
|
||||
|
||||
{if-no-resources-to-delete}
|
||||
*No resources will be deleted.*
|
||||
{end-if}
|
||||
|
||||
{end-if-what-if-succeeded}
|
||||
|
||||
{if-what-if-failed}
|
||||
### What-If Analysis Failed
|
||||
|
||||
The what-if operation could not complete. See the Issues section for details.
|
||||
{end-if}
|
||||
|
||||
---
|
||||
|
||||
## Recommendations
|
||||
|
||||
{generate-based-on-findings}
|
||||
|
||||
1. {recommendation-1}
|
||||
2. {recommendation-2}
|
||||
3. {recommendation-3}
|
||||
|
||||
---
|
||||
|
||||
## Next Steps
|
||||
|
||||
{if-all-passed}
|
||||
The preflight validation passed. You can proceed with deployment:
|
||||
|
||||
**For azd projects:**
|
||||
```bash
|
||||
azd provision
|
||||
# or
|
||||
azd up
|
||||
```
|
||||
|
||||
**For standalone Bicep:**
|
||||
```bash
|
||||
az deployment group create \
|
||||
--resource-group {rg-name} \
|
||||
--template-file {bicep-file} \
|
||||
--parameters {param-file}
|
||||
```
|
||||
{end-if}
|
||||
|
||||
{if-issues-exist}
|
||||
Please resolve the issues listed above before deploying. After fixes:
|
||||
|
||||
1. Re-run preflight validation to verify fixes
|
||||
2. Proceed with deployment once all checks pass
|
||||
{end-if}
|
||||
|
||||
---
|
||||
|
||||
*Report generated by Azure Deployment Preflight Skill*
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Status Values
|
||||
|
||||
### Overall Status
|
||||
|
||||
| Status | Meaning | Visual |
|
||||
|--------|---------|--------|
|
||||
| **Pass** | All checks succeeded, safe to deploy | ✅ |
|
||||
| **Pass with Warnings** | Checks succeeded but review warnings | ⚠️ |
|
||||
| **Fail** | One or more checks failed | ❌ |
|
||||
|
||||
### Individual Check Status
|
||||
|
||||
| Status | Meaning |
|
||||
|--------|---------|
|
||||
| ✅ Pass | Check completed successfully |
|
||||
| ❌ Fail | Check found errors |
|
||||
| ⚠️ Warnings | Check passed with warnings |
|
||||
| ⏭️ Skipped | Check was skipped (tool unavailable, etc.) |
|
||||
|
||||
---
|
||||
|
||||
## Example Report
|
||||
|
||||
```markdown
|
||||
# Azure Deployment Preflight Report
|
||||
|
||||
**Generated:** 2026-01-16T14:32:00Z
|
||||
**Status:** ⚠️ Pass with Warnings
|
||||
|
||||
---
|
||||
|
||||
## Summary
|
||||
|
||||
| Property | Value |
|
||||
|----------|-------|
|
||||
| **Template File(s)** | `infra/main.bicep` |
|
||||
| **Parameter File(s)** | `infra/main.bicepparam` |
|
||||
| **Project Type** | azd project |
|
||||
| **Deployment Scope** | subscription |
|
||||
| **Target** | my-subscription |
|
||||
| **Validation Level** | Provider |
|
||||
|
||||
### Validation Results
|
||||
|
||||
| Check | Status | Details |
|
||||
|-------|--------|---------|
|
||||
| Bicep Syntax | ✅ Pass | No errors found |
|
||||
| What-If Analysis | ⚠️ Warnings | 1 resource ignored due to nested template limits |
|
||||
| Permission Check | ✅ Pass | Full deployment permissions verified |
|
||||
|
||||
---
|
||||
|
||||
## Tools Executed
|
||||
|
||||
### Commands Run
|
||||
|
||||
| Step | Command | Exit Code | Duration |
|
||||
|------|---------|-----------|----------|
|
||||
| 1 | `bicep build infra/main.bicep --stdout` | 0 | 1.2s |
|
||||
| 2 | `azd provision --preview --environment dev` | 0 | 8.4s |
|
||||
|
||||
### Tool Versions
|
||||
|
||||
| Tool | Version |
|
||||
|------|---------|
|
||||
| Azure CLI | 2.76.0 |
|
||||
| Bicep CLI | 0.25.3 |
|
||||
| Azure Developer CLI | 1.9.0 |
|
||||
|
||||
---
|
||||
|
||||
## Issues
|
||||
|
||||
### Warnings
|
||||
|
||||
#### ⚠️ Nested Template Limit Reached
|
||||
|
||||
- **Severity:** Warning
|
||||
- **Source:** what-if
|
||||
- **Message:** 1 resource was ignored because nested template expansion limits were reached
|
||||
- **Recommendation:** Review the ignored resource manually after deployment
|
||||
|
||||
---
|
||||
|
||||
## What-If Results
|
||||
|
||||
### Change Summary
|
||||
|
||||
| Change Type | Count |
|
||||
|-------------|-------|
|
||||
| 🆕 Create | 3 |
|
||||
| 📝 Modify | 1 |
|
||||
| 🗑️ Delete | 0 |
|
||||
| ✓ No Change | 2 |
|
||||
| ⚠️ Ignore | 1 |
|
||||
|
||||
### Resources to Create
|
||||
|
||||
| Resource Type | Resource Name |
|
||||
|---------------|---------------|
|
||||
| Microsoft.Resources/resourceGroups | rg-myapp-dev |
|
||||
| Microsoft.Storage/storageAccounts | stmyappdev |
|
||||
| Microsoft.Web/sites | app-myapp-dev |
|
||||
|
||||
### Resources to Modify
|
||||
|
||||
#### Microsoft.KeyVault/vaults/kv-myapp-dev
|
||||
|
||||
| Property | Current Value | New Value |
|
||||
|----------|---------------|-----------|
|
||||
| properties.sku.name | standard | premium |
|
||||
| tags.environment | staging | dev |
|
||||
|
||||
### Resources to Delete
|
||||
|
||||
*No resources will be deleted.*
|
||||
|
||||
---
|
||||
|
||||
## Recommendations
|
||||
|
||||
1. Review the storage account name `stmyappdev` to ensure it meets naming requirements
|
||||
2. Confirm the Key Vault SKU upgrade from standard to premium is intentional
|
||||
3. The ignored nested template resource should be verified after deployment
|
||||
|
||||
---
|
||||
|
||||
## Next Steps
|
||||
|
||||
The preflight validation passed with warnings. Review the warnings above, then proceed:
|
||||
|
||||
```bash
|
||||
azd provision --environment dev
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
*Report generated by Azure Deployment Preflight Skill*
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Formatting Guidelines
|
||||
|
||||
1. **Use consistent emoji** for visual scanning
|
||||
2. **Include line numbers** when referencing Bicep errors
|
||||
3. **Provide actionable remediation** for each issue
|
||||
4. **Link to documentation** when available
|
||||
5. **Order issues by severity** (errors first, then warnings)
|
||||
6. **Include command examples** in Next Steps
|
||||
@@ -0,0 +1,379 @@
|
||||
# Validation Commands Reference
|
||||
|
||||
This reference documents all commands used for Azure deployment preflight validation.
|
||||
|
||||
## Azure Developer CLI (azd)
|
||||
|
||||
### azd provision --preview
|
||||
|
||||
Preview infrastructure changes for azd projects without deploying.
|
||||
|
||||
```bash
|
||||
azd provision --preview [options]
|
||||
```
|
||||
|
||||
**Options:**
|
||||
| Option | Description |
|
||||
|--------|-------------|
|
||||
| `--environment`, `-e` | Name of the environment to use |
|
||||
| `--no-prompt` | Accept defaults without prompting |
|
||||
| `--debug` | Enable debug logging |
|
||||
| `--cwd` | Set working directory |
|
||||
|
||||
**Examples:**
|
||||
|
||||
```bash
|
||||
# Preview with default environment
|
||||
azd provision --preview
|
||||
|
||||
# Preview specific environment
|
||||
azd provision --preview --environment dev
|
||||
|
||||
# Preview without prompts (CI/CD)
|
||||
azd provision --preview --no-prompt
|
||||
```
|
||||
|
||||
**Output:** Shows resources that will be created, modified, or deleted.
|
||||
|
||||
### azd auth login
|
||||
|
||||
Authenticate to Azure for azd operations.
|
||||
|
||||
```bash
|
||||
azd auth login [options]
|
||||
```
|
||||
|
||||
**Options:**
|
||||
| Option | Description |
|
||||
|--------|-------------|
|
||||
| `--check-status` | Check login status without logging in |
|
||||
| `--use-device-code` | Use device code flow |
|
||||
| `--tenant-id` | Specify tenant |
|
||||
| `--client-id` | Service principal client ID |
|
||||
|
||||
### azd env list
|
||||
|
||||
List available environments.
|
||||
|
||||
```bash
|
||||
azd env list
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Azure CLI (az)
|
||||
|
||||
### az deployment group what-if
|
||||
|
||||
Preview changes for resource group deployments.
|
||||
|
||||
```bash
|
||||
az deployment group what-if \
|
||||
--resource-group <rg-name> \
|
||||
--template-file <bicep-file> \
|
||||
[options]
|
||||
```
|
||||
|
||||
**Required Parameters:**
|
||||
| Parameter | Description |
|
||||
|-----------|-------------|
|
||||
| `--resource-group`, `-g` | Target resource group name |
|
||||
| `--template-file`, `-f` | Path to Bicep file |
|
||||
|
||||
**Optional Parameters:**
|
||||
| Parameter | Description |
|
||||
|-----------|-------------|
|
||||
| `--parameters`, `-p` | Parameter file or inline values |
|
||||
| `--validation-level` | `Provider` (default), `ProviderNoRbac`, or `Template` |
|
||||
| `--result-format` | `FullResourcePayloads` (default) or `ResourceIdOnly` |
|
||||
| `--no-pretty-print` | Output raw JSON for parsing |
|
||||
| `--name`, `-n` | Deployment name |
|
||||
| `--exclude-change-types` | Exclude specific change types from output |
|
||||
|
||||
**Validation Levels:**
|
||||
| Level | Description | Use Case |
|
||||
|-------|-------------|----------|
|
||||
| `Provider` | Full validation with RBAC checks | Default, most thorough |
|
||||
| `ProviderNoRbac` | Full validation, read permissions only | When lacking deploy permissions |
|
||||
| `Template` | Static syntax validation only | Quick syntax check |
|
||||
|
||||
**Examples:**
|
||||
|
||||
```bash
|
||||
# Basic what-if
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep
|
||||
|
||||
# With parameters and full validation
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--parameters main.bicepparam \
|
||||
--validation-level Provider
|
||||
|
||||
# Fallback without RBAC checks
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--validation-level ProviderNoRbac
|
||||
|
||||
# JSON output for parsing
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--no-pretty-print
|
||||
```
|
||||
|
||||
### az deployment sub what-if
|
||||
|
||||
Preview changes for subscription-level deployments.
|
||||
|
||||
```bash
|
||||
az deployment sub what-if \
|
||||
--location <location> \
|
||||
--template-file <bicep-file> \
|
||||
[options]
|
||||
```
|
||||
|
||||
**Required Parameters:**
|
||||
| Parameter | Description |
|
||||
|-----------|-------------|
|
||||
| `--location`, `-l` | Location for deployment metadata |
|
||||
| `--template-file`, `-f` | Path to Bicep file |
|
||||
|
||||
**Examples:**
|
||||
|
||||
```bash
|
||||
az deployment sub what-if \
|
||||
--location eastus \
|
||||
--template-file main.bicep \
|
||||
--parameters main.bicepparam \
|
||||
--validation-level Provider
|
||||
```
|
||||
|
||||
### az deployment mg what-if
|
||||
|
||||
Preview changes for management group deployments.
|
||||
|
||||
```bash
|
||||
az deployment mg what-if \
|
||||
--location <location> \
|
||||
--management-group-id <mg-id> \
|
||||
--template-file <bicep-file> \
|
||||
[options]
|
||||
```
|
||||
|
||||
**Required Parameters:**
|
||||
| Parameter | Description |
|
||||
|-----------|-------------|
|
||||
| `--location`, `-l` | Location for deployment metadata |
|
||||
| `--management-group-id`, `-m` | Target management group ID |
|
||||
| `--template-file`, `-f` | Path to Bicep file |
|
||||
|
||||
### az deployment tenant what-if
|
||||
|
||||
Preview changes for tenant-level deployments.
|
||||
|
||||
```bash
|
||||
az deployment tenant what-if \
|
||||
--location <location> \
|
||||
--template-file <bicep-file> \
|
||||
[options]
|
||||
```
|
||||
|
||||
**Required Parameters:**
|
||||
| Parameter | Description |
|
||||
|-----------|-------------|
|
||||
| `--location`, `-l` | Location for deployment metadata |
|
||||
| `--template-file`, `-f` | Path to Bicep file |
|
||||
|
||||
### az login
|
||||
|
||||
Authenticate to Azure CLI.
|
||||
|
||||
```bash
|
||||
az login [options]
|
||||
```
|
||||
|
||||
**Options:**
|
||||
| Option | Description |
|
||||
|--------|-------------|
|
||||
| `--tenant`, `-t` | Tenant ID or domain |
|
||||
| `--use-device-code` | Use device code flow |
|
||||
| `--service-principal` | Login as service principal |
|
||||
|
||||
### az account show
|
||||
|
||||
Display current subscription context.
|
||||
|
||||
```bash
|
||||
az account show
|
||||
```
|
||||
|
||||
### az group exists
|
||||
|
||||
Check if resource group exists.
|
||||
|
||||
```bash
|
||||
az group exists --name <rg-name>
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Bicep CLI
|
||||
|
||||
### bicep build
|
||||
|
||||
Compile Bicep to ARM JSON and validate syntax.
|
||||
|
||||
```bash
|
||||
bicep build <bicep-file> [options]
|
||||
```
|
||||
|
||||
**Options:**
|
||||
| Option | Description |
|
||||
|--------|-------------|
|
||||
| `--stdout` | Output to stdout instead of file |
|
||||
| `--outdir` | Output directory |
|
||||
| `--outfile` | Output file path |
|
||||
| `--no-restore` | Skip module restore |
|
||||
|
||||
**Examples:**
|
||||
|
||||
```bash
|
||||
# Validate syntax (output to stdout, no file created)
|
||||
bicep build main.bicep --stdout > /dev/null
|
||||
|
||||
# Build to specific directory
|
||||
bicep build main.bicep --outdir ./build
|
||||
|
||||
# Validate multiple files
|
||||
for f in *.bicep; do bicep build "$f" --stdout; done
|
||||
```
|
||||
|
||||
**Error Output Format:**
|
||||
```
|
||||
/path/to/file.bicep(22,51) : Error BCP064: Found unexpected tokens in interpolated expression.
|
||||
/path/to/file.bicep(22,51) : Error BCP004: The string at this location is not terminated.
|
||||
```
|
||||
|
||||
Format: `<file>(<line>,<column>) : <severity> <code>: <message>`
|
||||
|
||||
### bicep --version
|
||||
|
||||
Check Bicep CLI version.
|
||||
|
||||
```bash
|
||||
bicep --version
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Parameter File Detection
|
||||
|
||||
### Bicep Parameters (.bicepparam)
|
||||
|
||||
Modern Bicep parameter files (recommended):
|
||||
|
||||
```bicep
|
||||
using './main.bicep'
|
||||
|
||||
param location = 'eastus'
|
||||
param environment = 'dev'
|
||||
param tags = {
|
||||
environment: 'dev'
|
||||
project: 'myapp'
|
||||
}
|
||||
```
|
||||
|
||||
**Detection pattern:** `<template-name>.bicepparam`
|
||||
|
||||
### JSON Parameters (.parameters.json)
|
||||
|
||||
Traditional ARM parameter files:
|
||||
|
||||
```json
|
||||
{
|
||||
"$schema": "https://schema.management.azure.com/schemas/2019-04-01/deploymentParameters.json#",
|
||||
"contentVersion": "1.0.0.0",
|
||||
"parameters": {
|
||||
"location": { "value": "eastus" },
|
||||
"environment": { "value": "dev" }
|
||||
}
|
||||
}
|
||||
```
|
||||
|
||||
**Detection patterns:**
|
||||
- `<template-name>.parameters.json`
|
||||
- `parameters.json`
|
||||
- `parameters/<env>.json`
|
||||
|
||||
### Using Parameters with Commands
|
||||
|
||||
```bash
|
||||
# Bicep parameters file
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--parameters main.bicepparam
|
||||
|
||||
# JSON parameters file
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--parameters @parameters.json
|
||||
|
||||
# Inline parameter overrides
|
||||
az deployment group what-if \
|
||||
--resource-group my-rg \
|
||||
--template-file main.bicep \
|
||||
--parameters main.bicepparam \
|
||||
--parameters location=westus
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Determining Deployment Scope
|
||||
|
||||
Check the Bicep file's `targetScope` declaration:
|
||||
|
||||
```bicep
|
||||
// Resource Group (default if not specified)
|
||||
targetScope = 'resourceGroup'
|
||||
|
||||
// Subscription
|
||||
targetScope = 'subscription'
|
||||
|
||||
// Management Group
|
||||
targetScope = 'managementGroup'
|
||||
|
||||
// Tenant
|
||||
targetScope = 'tenant'
|
||||
```
|
||||
|
||||
**Scope to Command Mapping:**
|
||||
|
||||
| targetScope | Command | Required Parameters |
|
||||
|-------------|---------|---------------------|
|
||||
| `resourceGroup` | `az deployment group what-if` | `--resource-group` |
|
||||
| `subscription` | `az deployment sub what-if` | `--location` |
|
||||
| `managementGroup` | `az deployment mg what-if` | `--location`, `--management-group-id` |
|
||||
| `tenant` | `az deployment tenant what-if` | `--location` |
|
||||
|
||||
---
|
||||
|
||||
## Version Requirements
|
||||
|
||||
| Tool | Minimum Version | Recommended Version | Key Features |
|
||||
|------|-----------------|---------------------|--------------|
|
||||
| Azure CLI | 2.14.0 | 2.76.0+ | `--validation-level` switch |
|
||||
| Azure Developer CLI | 1.0.0 | Latest | `--preview` flag |
|
||||
| Bicep CLI | 0.4.0 | Latest | Best error messages |
|
||||
|
||||
**Check versions:**
|
||||
```bash
|
||||
az --version
|
||||
azd version
|
||||
bicep --version
|
||||
```
|
||||
276
skills/legacy-circuit-mockups/SKILL.md
Normal file
276
skills/legacy-circuit-mockups/SKILL.md
Normal file
@@ -0,0 +1,276 @@
|
||||
---
|
||||
name: legacy-circuit-mockups
|
||||
description: 'Generate breadboard circuit mockups and visual diagrams using HTML5 Canvas drawing techniques. Use when asked to create circuit layouts, visualize electronic component placements, draw breadboard diagrams, mockup 6502 builds, generate retro computer schematics, or design vintage electronics projects. Supports 555 timers, W65C02S microprocessors, 28C256 EEPROMs, W65C22 VIA chips, 7400-series logic gates, LEDs, resistors, capacitors, switches, buttons, crystals, and wires.'
|
||||
---
|
||||
|
||||
# Legacy Circuit Mockups
|
||||
|
||||
A skill for creating breadboard circuit mockups and visual diagrams for retro computing and electronics projects. This skill leverages HTML5 Canvas drawing mechanisms to render interactive circuit layouts featuring vintage components like the 6502 microprocessor, 555 timer ICs, EEPROMs, and 7400-series logic gates.
|
||||
|
||||
## When to Use This Skill
|
||||
|
||||
- User asks to "create a breadboard layout" or "mockup a circuit"
|
||||
- User wants to visualize component placement on a breadboard
|
||||
- User needs a visual reference for building a 6502 computer
|
||||
- User asks to "draw a circuit" or "diagram electronics"
|
||||
- User wants to create educational electronics visuals
|
||||
- User mentions Ben Eater tutorials or retro computing projects
|
||||
- User asks to mockup 555 timer circuits or LED projects
|
||||
- User needs to visualize wire connections between components
|
||||
|
||||
## Prerequisites
|
||||
|
||||
- Understanding of component pinouts from bundled reference files
|
||||
- Knowledge of breadboard layout conventions (rows, columns, power rails)
|
||||
|
||||
## Supported Components
|
||||
|
||||
### Microprocessors & Memory
|
||||
|
||||
| Component | Pins | Description |
|
||||
|-----------|------|-------------|
|
||||
| W65C02S | 40-pin DIP | 8-bit microprocessor with 16-bit address bus |
|
||||
| 28C256 | 28-pin DIP | 32KB parallel EEPROM |
|
||||
| W65C22 | 40-pin DIP | Versatile Interface Adapter (VIA) |
|
||||
| 62256 | 28-pin DIP | 32KB static RAM |
|
||||
|
||||
### Logic & Timer ICs
|
||||
|
||||
| Component | Pins | Description |
|
||||
|-----------|------|-------------|
|
||||
| NE555 | 8-pin DIP | Timer IC for timing and oscillation |
|
||||
| 7400 | 14-pin DIP | Quad 2-input NAND gate |
|
||||
| 7402 | 14-pin DIP | Quad 2-input NOR gate |
|
||||
| 7404 | 14-pin DIP | Hex inverter (NOT gate) |
|
||||
| 7408 | 14-pin DIP | Quad 2-input AND gate |
|
||||
| 7432 | 14-pin DIP | Quad 2-input OR gate |
|
||||
|
||||
### Passive & Active Components
|
||||
|
||||
| Component | Description |
|
||||
|-----------|-------------|
|
||||
| LED | Light emitting diode (various colors) |
|
||||
| Resistor | Current limiting (configurable values) |
|
||||
| Capacitor | Filtering and timing (ceramic/electrolytic) |
|
||||
| Crystal | Clock oscillator |
|
||||
| Switch | Toggle switch (latching) |
|
||||
| Button | Momentary push button |
|
||||
| Potentiometer | Variable resistor |
|
||||
| Photoresistor | Light-dependent resistor |
|
||||
|
||||
### Grid System
|
||||
|
||||
```javascript
|
||||
// Standard breadboard grid: 20px spacing
|
||||
const gridSize = 20;
|
||||
const cellX = Math.floor(x / gridSize) * gridSize;
|
||||
const cellY = Math.floor(y / gridSize) * gridSize;
|
||||
```
|
||||
|
||||
### Component Rendering Pattern
|
||||
|
||||
```javascript
|
||||
// All components follow this structure:
|
||||
{
|
||||
type: 'component-type',
|
||||
x: gridX,
|
||||
y: gridY,
|
||||
width: componentWidth,
|
||||
height: componentHeight,
|
||||
rotation: 0, // 0, 90, 180, 270
|
||||
properties: { /* component-specific data */ }
|
||||
}
|
||||
```
|
||||
|
||||
### Wire Connections
|
||||
|
||||
```javascript
|
||||
// Wire connection format:
|
||||
{
|
||||
start: { x: startX, y: startY },
|
||||
end: { x: endX, y: endY },
|
||||
color: '#ff0000' // Wire color coding
|
||||
}
|
||||
```
|
||||
|
||||
## Step-by-Step Workflows
|
||||
|
||||
### Creating a Basic LED Circuit Mockup
|
||||
|
||||
1. Define breadboard dimensions and grid
|
||||
2. Place power rail connections (+5V and GND)
|
||||
3. Add LED component with anode/cathode orientation
|
||||
4. Place current-limiting resistor
|
||||
5. Draw wire connections between components
|
||||
6. Add labels and annotations
|
||||
|
||||
### Creating a 555 Timer Circuit
|
||||
|
||||
1. Place NE555 IC on breadboard (pins 1-4 left, 5-8 right)
|
||||
2. Connect pin 1 (GND) to ground rail
|
||||
3. Connect pin 8 (Vcc) to power rail
|
||||
4. Add timing resistors and capacitors
|
||||
5. Wire trigger and threshold connections
|
||||
6. Connect output to LED or other load
|
||||
|
||||
### Creating a 6502 Microprocessor Layout
|
||||
|
||||
1. Place W65C02S centered on breadboard
|
||||
2. Add 28C256 EEPROM for program storage
|
||||
3. Place W65C22 VIA for I/O
|
||||
4. Add 7400-series logic for address decoding
|
||||
5. Wire address bus (A0-A15)
|
||||
6. Wire data bus (D0-D7)
|
||||
7. Connect control signals (R/W, PHI2, RESB)
|
||||
8. Add reset button and clock crystal
|
||||
|
||||
## Component Pinout Quick Reference
|
||||
|
||||
### 555 Timer (8-pin DIP)
|
||||
|
||||
| Pin | Name | Function |
|
||||
|:---:|:-----|:---------|
|
||||
| 1 | GND | Ground (0V) |
|
||||
| 2 | TRIG | Trigger (< 1/3 Vcc starts timing) |
|
||||
| 3 | OUT | Output (source/sink 200mA) |
|
||||
| 4 | RESET | Active-low reset |
|
||||
| 5 | CTRL | Control voltage (bypass with 10nF) |
|
||||
| 6 | THR | Threshold (> 2/3 Vcc resets) |
|
||||
| 7 | DIS | Discharge (open collector) |
|
||||
| 8 | Vcc | Supply (+4.5V to +16V) |
|
||||
|
||||
### W65C02S (40-pin DIP) - Key Pins
|
||||
|
||||
| Pin | Name | Function |
|
||||
|:---:|:-----|:---------|
|
||||
| 8 | VDD | Power supply |
|
||||
| 21 | VSS | Ground |
|
||||
| 37 | PHI2 | System clock input |
|
||||
| 40 | RESB | Active-low reset |
|
||||
| 34 | RWB | Read/Write signal |
|
||||
| 9-25 | A0-A15 | Address bus |
|
||||
| 26-33 | D0-D7 | Data bus |
|
||||
|
||||
### 28C256 EEPROM (28-pin DIP) - Key Pins
|
||||
|
||||
| Pin | Name | Function |
|
||||
|:---:|:-----|:---------|
|
||||
| 14 | GND | Ground |
|
||||
| 28 | VCC | Power supply |
|
||||
| 20 | CE | Chip enable (active-low) |
|
||||
| 22 | OE | Output enable (active-low) |
|
||||
| 27 | WE | Write enable (active-low) |
|
||||
| 1-10, 21-26 | A0-A14 | Address inputs |
|
||||
| 11-19 | I/O0-I/O7 | Data bus |
|
||||
|
||||
## Formulas Reference
|
||||
|
||||
### Resistor Calculations
|
||||
|
||||
- **Ohm's Law:** V = I × R
|
||||
- **LED Current:** R = (Vcc - Vled) / Iled
|
||||
- **Power:** P = V × I = I² × R
|
||||
|
||||
### 555 Timer Formulas
|
||||
|
||||
**Astable Mode:**
|
||||
|
||||
- Frequency: f = 1.44 / ((R1 + 2×R2) × C)
|
||||
- High time: t₁ = 0.693 × (R1 + R2) × C
|
||||
- Low time: t₂ = 0.693 × R2 × C
|
||||
- Duty cycle: D = (R1 + R2) / (R1 + 2×R2) × 100%
|
||||
|
||||
**Monostable Mode:**
|
||||
|
||||
- Pulse width: T = 1.1 × R × C
|
||||
|
||||
### Capacitor Calculations
|
||||
|
||||
- Capacitive reactance: Xc = 1 / (2πfC)
|
||||
- Energy stored: E = ½ × C × V²
|
||||
|
||||
## Color Coding Conventions
|
||||
|
||||
### Wire Colors
|
||||
|
||||
| Color | Purpose |
|
||||
|-------|---------|
|
||||
| Red | +5V / Power |
|
||||
| Black | Ground |
|
||||
| Yellow | Clock / Timing |
|
||||
| Blue | Address bus |
|
||||
| Green | Data bus |
|
||||
| Orange | Control signals |
|
||||
| White | General purpose |
|
||||
|
||||
### LED Colors
|
||||
|
||||
| Color | Forward Voltage |
|
||||
|-------|-----------------|
|
||||
| Red | 1.8V - 2.2V |
|
||||
| Green | 2.0V - 2.2V |
|
||||
| Yellow | 2.0V - 2.2V |
|
||||
| Blue | 3.0V - 3.5V |
|
||||
| White | 3.0V - 3.5V |
|
||||
|
||||
## Build Examples
|
||||
|
||||
### Build 1 — Single LED
|
||||
|
||||
**Components:** Red LED, 220Ω resistor, jumper wires, power source
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert black jumper wire from power GND to row A5
|
||||
2. Insert red jumper wire from power +5V to row J5
|
||||
3. Place LED with cathode (short leg) in row aligned with GND
|
||||
4. Place 220Ω resistor between power and LED anode
|
||||
|
||||
### Build 2 — 555 Astable Blinker
|
||||
|
||||
**Components:** NE555, LED, resistors (10kΩ, 100kΩ), capacitor (10µF)
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Place 555 IC straddling center channel
|
||||
2. Connect pin 1 to GND, pin 8 to +5V
|
||||
3. Connect pin 4 to pin 8 (disable reset)
|
||||
4. Wire 10kΩ between pin 7 and +5V
|
||||
5. Wire 100kΩ between pins 6 and 7
|
||||
6. Wire 10µF between pin 6 and GND
|
||||
7. Connect pin 3 (output) to LED circuit
|
||||
|
||||
## Troubleshooting
|
||||
|
||||
| Issue | Solution |
|
||||
|-------|----------|
|
||||
| LED doesn't light | Check polarity (anode to +, cathode to -) |
|
||||
| Circuit doesn't power | Verify power rail connections |
|
||||
| IC not working | Check VCC and GND pin connections |
|
||||
| 555 not oscillating | Verify threshold/trigger capacitor wiring |
|
||||
| Microprocessor stuck | Check RESB is HIGH after reset pulse |
|
||||
|
||||
## References
|
||||
|
||||
Detailed component specifications are available in the bundled reference files:
|
||||
|
||||
- [555.md](references/555.md) - Complete 555 timer IC specification
|
||||
- [6502.md](references/6502.md) - MOS 6502 microprocessor details
|
||||
- [6522.md](references/6522.md) - W65C22 VIA interface adapter
|
||||
- [28256-eeprom.md](references/28256-eeprom.md) - AT28C256 EEPROM specification
|
||||
- [6C62256.md](references/6C62256.md) - 62256 SRAM details
|
||||
- [7400-series.md](references/7400-series.md) - TTL logic gate pinouts
|
||||
- [assembly-compiler.md](references/assembly-compiler.md) - Assembly compiler specification
|
||||
- [assembly-language.md](references/assembly-language.md) - Assembly language specification
|
||||
- [basic-electronic-components.md](references/basic-electronic-components.md) - Resistors, capacitors, switches
|
||||
- [breadboard.md](references/breadboard.md) - Breadboard specifications
|
||||
- [common-breadboard-components.md](references/common-breadboard-components.md) - Comprehensive component reference
|
||||
- [connecting-electronic-components.md](references/connecting-electronic-components.md) - Step-by-step build guides
|
||||
- [emulator-28256-eeprom.md](references/emulator-28256-eeprom.md) - Emulating 28256-eeprom specification
|
||||
- [emulator-6502.md](references/emulator-6502.md) - Emulating 6502 specification
|
||||
- [emulator-6522.md](references/emulator-6522.md) - Emulating 6522 specification
|
||||
- [emulator-6C62256.md](references/emulator-6C62256.md) - Emulating 6C62256 specification
|
||||
- [emulator-lcd.md](references/emulator-lcd.md) - Emulating a LCD specification
|
||||
- [lcd.md](references/lcd.md) - LCD display interfacing
|
||||
- [minipro.md](references/minipro.md) - EEPROM programmer usage
|
||||
- [t48eeprom-programmer.md](references/t48eeprom-programmer.md) - T48 programmer reference
|
||||
190
skills/legacy-circuit-mockups/references/28256-eeprom.md
Normal file
190
skills/legacy-circuit-mockups/references/28256-eeprom.md
Normal file
@@ -0,0 +1,190 @@
|
||||
# AT28C256 256K (32K x 8) Parallel EEPROM Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **AT28C256** is a non-volatile, electrically erasable and programmable read-only memory (EEPROM) manufactured by Atmel (now Microchip). It provides **256 Kbits** of storage organized as **32,768 x 8 bits** and is commonly used in 8-bit microprocessor systems such as those based on the **6502**, **Z80**, and similar CPUs.
|
||||
|
||||
The device supports byte-level write operations, fast read access, and software-controlled data protection.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| -------------- | ------------------------------ |
|
||||
| Memory size | 256 Kbits (32 KB) |
|
||||
| Organization | 32,768 x 8 bits |
|
||||
| Data bus | 8-bit |
|
||||
| Address bus | 15-bit (A0-A14) |
|
||||
| Technology | EEPROM |
|
||||
| Endurance | ≥ 100,000 write cycles |
|
||||
| Data retention | ≥ 10 years |
|
||||
| Access time | 150-250 ns (variant dependent) |
|
||||
| Package types | DIP-28, PLCC-32, TSOP |
|
||||
|
||||
---
|
||||
|
||||
## 3. Pin Configuration (Logical)
|
||||
|
||||
### 3.1 Address Pins (A0-A14)
|
||||
|
||||
* Select one of 32,768 memory locations
|
||||
|
||||
### 3.2 Data Pins (I/O0-I/O7)
|
||||
|
||||
* Bidirectional tri-state data bus
|
||||
* Outputs valid during read cycles
|
||||
|
||||
### 3.3 Control Pins
|
||||
|
||||
| Pin | Description |
|
||||
| --- | -------------------------- |
|
||||
| CE | Chip Enable (active low) |
|
||||
| OE | Output Enable (active low) |
|
||||
| WE | Write Enable (active low) |
|
||||
| VCC | +5 V power supply |
|
||||
| GND | Ground |
|
||||
|
||||
---
|
||||
|
||||
## 4. Memory Organization
|
||||
|
||||
* Linear address space from `$0000` to `$7FFF`
|
||||
* Each address corresponds to one 8-bit byte
|
||||
|
||||
```text
|
||||
Address Range: 0000h - 7FFFh
|
||||
Data Width: 8 bits
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 5. Read Operation
|
||||
|
||||
### 5.1 Read Cycle Conditions
|
||||
|
||||
| Signal | State |
|
||||
| ------ | ----- |
|
||||
| CE | LOW |
|
||||
| OE | LOW |
|
||||
| WE | HIGH |
|
||||
|
||||
* Data appears on I/O pins after access time
|
||||
* Output remains valid while CE and OE are asserted
|
||||
* Outputs are high-impedance when CE or OE is HIGH
|
||||
|
||||
---
|
||||
|
||||
## 6. Write Operation
|
||||
|
||||
### 6.1 Byte Write Cycle
|
||||
|
||||
| Signal | State |
|
||||
| ------ | --------- |
|
||||
| CE | LOW |
|
||||
| OE | HIGH |
|
||||
| WE | LOW pulse |
|
||||
|
||||
* Address and data must be stable during WE low pulse
|
||||
* Internal write cycle time ≈ 10 ms (max)
|
||||
* Device automatically handles erase-before-write
|
||||
|
||||
---
|
||||
|
||||
## 7. Software Data Protection (SDP)
|
||||
|
||||
The AT28C256 includes optional **Software Data Protection** to prevent accidental writes.
|
||||
|
||||
### 7.1 SDP Enable Sequence
|
||||
|
||||
```text
|
||||
Write $AA to address $5555
|
||||
Write $55 to address $2AAA
|
||||
Write $A0 to address $5555
|
||||
```
|
||||
|
||||
### 7.2 SDP Disable Sequence
|
||||
|
||||
```text
|
||||
Write $AA to address $5555
|
||||
Write $55 to address $2AAA
|
||||
Write $80 to address $5555
|
||||
Write $AA to address $5555
|
||||
Write $55 to address $2AAA
|
||||
Write $20 to address $5555
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 8. Write Cycle Timing Notes
|
||||
|
||||
* Writes are internally timed; no external polling required
|
||||
* During write cycle, reads return undefined data
|
||||
* Device ignores additional write attempts while busy
|
||||
|
||||
---
|
||||
|
||||
## 9. Data Polling (Optional)
|
||||
|
||||
* I/O7 may be monitored during write
|
||||
* When I/O7 matches written data, write is complete
|
||||
|
||||
---
|
||||
|
||||
## 10. Reset and Power Behavior
|
||||
|
||||
* No explicit reset pin
|
||||
* Writes inhibited during power-up and power-down
|
||||
* Outputs default to high-impedance until CE and OE asserted
|
||||
|
||||
---
|
||||
|
||||
## 11. Typical System Integration (6502 Example)
|
||||
|
||||
```text
|
||||
Address Range: $8000 - $FFFF
|
||||
A15 used as chip select
|
||||
OE R/W?
|
||||
WE inverted R/W?
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 12. Absolute Maximum Ratings (Summary)
|
||||
|
||||
| Parameter | Rating |
|
||||
| ------------- | --------------------- |
|
||||
| VCC | -0.6 V to +6.25 V |
|
||||
| Input voltage | -0.6 V to VCC + 0.6 V |
|
||||
| Storage temp | -65 °C to +150 °C |
|
||||
|
||||
---
|
||||
|
||||
## 13. Variants and Compatible Devices
|
||||
|
||||
| Device | Notes |
|
||||
| ---------------- | ---------------------------- |
|
||||
| AT28C256 | Original Atmel |
|
||||
| AT28C256F | Faster access time |
|
||||
| SST28SF256 | Flash-compatible alternative |
|
||||
| 28C256 (generic) | Common pin-compatible EEPROM |
|
||||
|
||||
---
|
||||
|
||||
## 14. Common Use Cases
|
||||
|
||||
* ROM replacement in retro systems
|
||||
* Firmware storage
|
||||
* Microcomputer monitors and BASIC ROMs
|
||||
* Prototyping and hobbyist computers
|
||||
|
||||
---
|
||||
|
||||
## 15. References
|
||||
|
||||
* <https://www.utmel.com/components/at28bv256-eeproms-pinout-equivalent-and-datasheet?id=1019>
|
||||
* <https://www.futurlec.com/Memory/28C256.shtml>
|
||||
* <https://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf>
|
||||
* <https://bread80.com/2020/08/10/the-ben-eater-eeprom-programmer-28c256-and-software-data-protection/>
|
||||
|
||||
---
|
||||
861
skills/legacy-circuit-mockups/references/555.md
Normal file
861
skills/legacy-circuit-mockups/references/555.md
Normal file
@@ -0,0 +1,861 @@
|
||||
# 555
|
||||
|
||||
[www.fairchildsemi.com](www.fairchildsemi.com)
|
||||
|
||||
The LM555/NE555/SA555 is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the time delay is controlled by one external resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.
|
||||
|
||||
## Features
|
||||
|
||||
- High Current Drive Capability (200mA)
|
||||
- Adjustable Duty Cycle
|
||||
- Temperature Stability of 0.005%/°C
|
||||
- Timing From μSec to Hours
|
||||
- Turn off Time Less Than 2μSec
|
||||
|
||||
## Applications
|
||||
|
||||
- Precision Timing
|
||||
- Pulse Generation
|
||||
- Time Delay Generation
|
||||
- Sequential Timing
|
||||
|
||||
## Internal Block Diagram
|
||||
|
||||
```mermaid
|
||||
flowchart TB
|
||||
subgraph IC["555 Timer IC"]
|
||||
direction TB
|
||||
|
||||
subgraph DIVIDER["Voltage Divider"]
|
||||
R1["R (5kΩ)"]
|
||||
R2["R (5kΩ)"]
|
||||
R3["R (5kΩ)"]
|
||||
R1 --- R2 --- R3
|
||||
end
|
||||
|
||||
COMP1["Comparator 1<br/>(Threshold)"]
|
||||
COMP2["Comparator 2<br/>(Trigger)"]
|
||||
FF["Flip-Flop<br/>S-R"]
|
||||
OUT_STAGE["Output<br/>Stage"]
|
||||
DISCH_TR["Discharge<br/>Transistor"]
|
||||
VREF["Vref"]
|
||||
end
|
||||
|
||||
PIN8["Pin 8<br/>Vcc"] --> R1
|
||||
R3 --> PIN1["Pin 1<br/>GND"]
|
||||
|
||||
R1 -.->|"2/3 Vcc"| COMP1
|
||||
R2 -.->|"1/3 Vcc"| COMP2
|
||||
|
||||
PIN6["Pin 6<br/>Threshold"] --> COMP1
|
||||
PIN2["Pin 2<br/>Trigger"] --> COMP2
|
||||
|
||||
COMP1 -->|R| FF
|
||||
COMP2 -->|S| FF
|
||||
|
||||
FF --> OUT_STAGE
|
||||
FF --> DISCH_TR
|
||||
|
||||
OUT_STAGE --> PIN3["Pin 3<br/>Output"]
|
||||
DISCH_TR --> PIN7["Pin 7<br/>Discharge"]
|
||||
|
||||
PIN4["Pin 4<br/>Reset"] --> FF
|
||||
PIN5["Pin 5<br/>Control Voltage"] -.-> R2
|
||||
|
||||
style PIN1 fill:#000,color:#fff
|
||||
style PIN2 fill:#f96,color:#000
|
||||
style PIN3 fill:#6f6,color:#000
|
||||
style PIN4 fill:#f66,color:#000
|
||||
style PIN5 fill:#ff6,color:#000
|
||||
style PIN6 fill:#6ff,color:#000
|
||||
style PIN7 fill:#f6f,color:#000
|
||||
style PIN8 fill:#f00,color:#fff
|
||||
```
|
||||
|
||||
**Pin Configuration:**
|
||||
|
||||
| Pin | Name | Function |
|
||||
|:---:|:---|:---|
|
||||
| 1 | GND | Ground reference |
|
||||
| 2 | TRIG | Trigger input (< 1/3 Vcc starts timing) |
|
||||
| 3 | OUT | Output (high or low) |
|
||||
| 4 | RESET | Active low reset |
|
||||
| 5 | CONT | Control voltage (2/3 Vcc reference) |
|
||||
| 6 | THRES | Threshold input (> 2/3 Vcc ends timing) |
|
||||
| 7 | DISCH | Discharge (open collector) |
|
||||
| 8 | Vcc | Supply voltage (+4.5V to +16V) |
|
||||
|
||||
## Absolute Maximum Ratings (Ta = 25°C)
|
||||
|
||||
| Parameter | Symbol | Value | Unit |
|
||||
| :--- | :--- | :--- | :--- |
|
||||
| Supply Voltage | Vcc | 16 | V |
|
||||
| Lead temperature (soldering 10 sec) | Tled | 300 | °C |
|
||||
| Power Dissipation | PD | 600 | mW |
|
||||
| Operating Temperature Range<br>LM555/NE555<br>SA555 | Topr | - 65 ~ + 150 | °C |
|
||||
|
||||
## Electrical Characteristics
|
||||
|
||||
(TA = 250C, vcc = 5 15V, unless otherwise specified)
|
||||
|
||||
| Parameter | Symbol | Conditions | Min. | Typ. | Max. | Unit |
|
||||
| :--- | :--- | :--- | :--- |:--- | :--- | :--- |
|
||||
| Supply Voltage | vcc | - | 4.5 | - | 16 | V |
|
||||
| Supply Current (Low Stable) (Note 1) | Icc | Vcc = 5V, Rl = ∞<hr>Vcc = 15V, Rl = ∞ | -<hr>- | 3<hr>7.5 | 6<hr>15 | mA<hr>mA |
|
||||
| Timing Error (Monostable)<br>Initial Accuracy (Note2)<br>Drift with Temperature (Note4)<br>Drift with Supply Voltage (Note4)<br> | ACCUR<br>Δt/ΔT<br>Δt/ΔVcc | Ra = 1kΩ to100kΩ<br>C = 0.1μF | - | 1.0<br>50<br>0.1 | 3.0<br><br>0.5 | %<br>ppm/°C<br>%/V |
|
||||
| Timing Error (Astable)<br>Initial Accuracy (Note2)<br>Drift with Temperature (Note4)<br>Drift with Supply Voltage (Note4) | ACCUR<br>Δt/ΔT<br>Δt/ΔVcc | Ra = 1kΩ to 100kΩ<br> C = 0.1μF | - | 2.25<br>150<br>0.3 | - | %<br>ppm/°C<br>%/V |
|
||||
| Control Voltage | Vc | Vcc = 15V<hr> Vcc = 5V | 9.0<hr>2.6 | 10.0<hr>3.33 | 11.0<hr>4.0 | V<hr>V |
|
||||
| Threshold Voltage | VTH | VCC = 15V<hr>VCC = 5V | -<hr>- | 10.0<hr>3.33 | -<hr>- | V<hr>V |
|
||||
| Threshold Current (Note3) | Ith | - | - | 0.1 | 0.25 | μA |
|
||||
| Trigger Voltage | VTR | VCC = 5V<hr>VCC = 15V | 1.1<hr>4.5 | 1.67<hr>5 | 2.2<hr>5.6 | V<hr>V |
|
||||
| Trigger Current | ITR | VTR = 0V | 0.01 | 2.0 | μA |
|
||||
| Reset Voltage | VRST | - | 0.4 | 0.7 | 1.0 | V |
|
||||
| Reset Current | IRST | - | 0.1 | 0.4 | mA |
|
||||
| Low Output Voltage | VOL | VCC = 15V<br>ISINK = 10mA<br>ISINK = 50mA<hr>VCC = 5V<br>ISINK = 5mA | -<hr>- | 0.06<br>0.3<hr>0.05 | 0.25<br>0.75<hr>0.35 | V<br>V<hr>V |
|
||||
| High Output Voltage | VOH | VCC = 15V<br>ISOURCE = 200mA<br>ISOURCE = 100mA<hr>VCC = 5V<br>ISOURCE = 100mA | 12.75<hr>2.75 | 12.5<br>13.3<hr>3.3 | -<hr>- | V<br>V<hr>V |
|
||||
| Rise Time of Output (Note4) | tR | - | - | 100 | - | ns |
|
||||
| Fall Time of Output (Note4) | tF | - | - | 100 | - | ns |
|
||||
| Discharge Leakage Current | ILKG | - | - | 20 | 100 | nA |
|
||||
|
||||
**Notes:**
|
||||
|
||||
1. When the output is high. the supply current is typically 1mA less than at VCC = 5V.
|
||||
2. Tested at VCC = 5.0V and VCC = 15V.
|
||||
3. This will determine the maximum value of RA + RB for 15V operation, the max- total R = 20MQ. and for 5V operation, the max/
|
||||
- total R 8.7MΩ
|
||||
4. These parameters, although guaranteed. are not 100% tested in production.
|
||||
|
||||
## Application Information
|
||||
|
||||
Table 1 below is the basic operating table of 555 timer:
|
||||
|
||||
| Threshold Voltage<br>(Vth)(PIN 6) | Trigger Voltage<br>(Vtr)(PIN 2) | Reset(PIN 4) | Output(PIN 3) | Discharging Tr.<br>(PIN 7) |
|
||||
| :--- | :--- | :--- | :--- | :--- |
|
||||
| Don't care | Don't care | Low | Low | ON |
|
||||
| Vth > 2Vcc / 3 | Vth > 2Vcc / 3 | High | Low | ON |
|
||||
| Vcc / 3 < Vth < 2 Vcc / 3 | Vcc / 3 < Vth < 2 Vcc / 3 | High | - | - |
|
||||
| Vth < Vcc / 3 | Vth < Vcc / 3 | High | High | OFF |
|
||||
|
||||
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
|
||||
|
||||
### 1. Monostable Operation
|
||||
|
||||
#### Figure 1. Monostable Circuit
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
subgraph CIRCUIT["Monostable Configuration"]
|
||||
VCC["+Vcc"]
|
||||
|
||||
subgraph TIMER["555 Timer"]
|
||||
P4["4<br/>RESET"]
|
||||
P8["8<br/>Vcc"]
|
||||
P7["7<br/>DISCH"]
|
||||
P2["2<br/>TRIG"]
|
||||
P6["6<br/>THRES"]
|
||||
P3["3<br/>OUT"]
|
||||
P5["5<br/>CONT"]
|
||||
P1["1<br/>GND"]
|
||||
end
|
||||
|
||||
RA["RA"]
|
||||
C1["C1"]
|
||||
C2["C2<br/>0.01μF"]
|
||||
RL["RL"]
|
||||
GND["GND"]
|
||||
end
|
||||
|
||||
VCC --> P4
|
||||
VCC --> P8
|
||||
VCC --> RA
|
||||
RA --> P7
|
||||
P7 --> P6
|
||||
P6 --> C1
|
||||
C1 --> GND
|
||||
|
||||
TRIG_IN["Trigger<br/>Input"] --> P2
|
||||
|
||||
P3 --> RL
|
||||
RL --> OUTPUT["Output"]
|
||||
|
||||
P5 --> C2
|
||||
C2 --> GND
|
||||
P1 --> GND
|
||||
|
||||
style VCC fill:#f00,color:#fff
|
||||
style GND fill:#000,color:#fff
|
||||
style TRIG_IN fill:#f96
|
||||
style OUTPUT fill:#6f6
|
||||
```
|
||||
|
||||
**Component Values:**
|
||||
|
||||
- RA: Timing resistor (1kΩ to 10MΩ typical)
|
||||
- C1: Timing capacitor
|
||||
- C2: Bypass capacitor (0.01μF recommended)
|
||||
- RL: Load resistor
|
||||
|
||||
**Time Delay Formula:**
|
||||
$$t_d = 1.1 \times R_A \times C_1$$
|
||||
|
||||
#### Figure 2. Resistance and Capacitance vs. Time Delay (td)
|
||||
|
||||
```mermaid
|
||||
%%{init: {'theme': 'base', 'themeVariables': { 'primaryColor': '#fff', 'lineColor': '#333'}}}%%
|
||||
xychart-beta
|
||||
title "Time Delay vs Capacitance (Log Scale)"
|
||||
x-axis "Time Delay (seconds)" [0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10, 100]
|
||||
y-axis "Capacitance (μF)" 0.001 --> 1000
|
||||
line "R=1kΩ" [0.001, 0.01, 0.1, 1, 10, 100, 1000, 10000]
|
||||
line "R=10kΩ" [0.0001, 0.001, 0.01, 0.1, 1, 10, 100, 1000]
|
||||
line "R=100kΩ" [0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10, 100]
|
||||
line "R=1MΩ" [0.000001, 0.00001, 0.0001, 0.001, 0.01, 0.1, 1, 10]
|
||||
```
|
||||
|
||||
| RA | C1 | Time Delay (td) |
|
||||
|:---|:---|:---|
|
||||
| 1 kΩ | 0.1 μF | 110 μs |
|
||||
| 10 kΩ | 0.1 μF | 1.1 ms |
|
||||
| 100 kΩ | 0.1 μF | 11 ms |
|
||||
| 1 MΩ | 1 μF | 1.1 s |
|
||||
| 10 MΩ | 10 μF | 110 s |
|
||||
|
||||
#### Figure 3. Waveforms of Monostable Operation
|
||||
|
||||
```mermaid
|
||||
%%{init: {'theme': 'base'}}%%
|
||||
gantt
|
||||
title Monostable Waveforms (Normal Operation)
|
||||
dateFormat X
|
||||
axisFormat %s
|
||||
|
||||
section Trigger
|
||||
High (Vcc) :a1, 0, 2
|
||||
Low (<Vcc/3) :crit, a2, 2, 3
|
||||
High (Vcc) :a3, 3, 10
|
||||
|
||||
section Output
|
||||
Low (0V) :b1, 0, 2
|
||||
High (Vcc) :active, b2, 2, 8
|
||||
Low (0V) :b3, 8, 10
|
||||
|
||||
section Threshold (Vc1)
|
||||
Charging :c1, 2, 8
|
||||
```
|
||||
|
||||
```
|
||||
Trigger ─────┐ ┌─────────────────────
|
||||
(Pin 2) └─────┘
|
||||
↓ Trigger pulse
|
||||
|
||||
Output ─────────┐ ┌───────────
|
||||
(Pin 3) └──────────┘
|
||||
|←── td ───→|
|
||||
|
||||
Threshold /‾‾‾‾‾‾‾‾\
|
||||
(Pin 6) ─────/ \────────────
|
||||
0V ↗ ↘
|
||||
Vcc/3 2Vcc/3
|
||||
|
||||
td = 1.1 × RA × C1
|
||||
```
|
||||
|
||||
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3 at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on RA and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.
|
||||
|
||||
#### Figure 4. Waveforms of Monostable Operation (abnormal)
|
||||
|
||||
```
|
||||
Trigger ─────┐ ┌──┐ ┌─────────────────
|
||||
(Pin 2) └──┘ └──┘
|
||||
↓ ↓ Retriggering during output high
|
||||
|
||||
Output ─────────┐ ┌─────
|
||||
(Pin 3) └────────────────┘
|
||||
|←── extended td ──→|
|
||||
|
||||
Threshold /‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\
|
||||
(Pin 6) ─────/ \────
|
||||
0V ↗ ↘
|
||||
Vcc/3 2Vcc/3
|
||||
|
||||
⚠️ ABNORMAL: Trigger held low extends output pulse!
|
||||
Trigger must return high before output goes low.
|
||||
```
|
||||
|
||||
**Note:** For normal operation, the trigger pulse voltage must return above Vcc/3 before the timer output goes low. If the trigger remains below Vcc/3, the output pulse will be extended abnormally.
|
||||
|
||||
### 2. Astable Operation
|
||||
|
||||
#### Figure 5. Astable Circuit
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
subgraph CIRCUIT["Astable Configuration"]
|
||||
VCC["+Vcc"]
|
||||
|
||||
subgraph TIMER["555 Timer"]
|
||||
P4["4<br/>RESET"]
|
||||
P8["8<br/>Vcc"]
|
||||
P7["7<br/>DISCH"]
|
||||
P2["2<br/>TRIG"]
|
||||
P6["6<br/>THRES"]
|
||||
P3["3<br/>OUT"]
|
||||
P5["5<br/>CONT"]
|
||||
P1["1<br/>GND"]
|
||||
end
|
||||
|
||||
RA["RA"]
|
||||
RB["RB"]
|
||||
C1["C1"]
|
||||
C2["C2<br/>0.01μF"]
|
||||
GND["GND"]
|
||||
end
|
||||
|
||||
VCC --> P4
|
||||
VCC --> P8
|
||||
VCC --> RA
|
||||
RA --> P7
|
||||
P7 --> RB
|
||||
RB --> P6
|
||||
RB --> P2
|
||||
P6 --> C1
|
||||
C1 --> GND
|
||||
|
||||
P3 --> OUTPUT["Output"]
|
||||
|
||||
P5 --> C2
|
||||
C2 --> GND
|
||||
P1 --> GND
|
||||
|
||||
MOD["Modulation<br/>(optional)"] -.-> P5
|
||||
|
||||
style VCC fill:#f00,color:#fff
|
||||
style GND fill:#000,color:#fff
|
||||
style OUTPUT fill:#6f6
|
||||
style MOD fill:#ff6
|
||||
```
|
||||
|
||||
**Component Values:**
|
||||
|
||||
- RA: Charge resistor (controls HIGH time)
|
||||
- RB: Charge/discharge resistor (affects both HIGH and LOW times)
|
||||
- C1: Timing capacitor
|
||||
- C2: Bypass capacitor (0.01μF recommended)
|
||||
|
||||
**Timing Formulas:**
|
||||
|
||||
- High time: $t_H = 0.693 \times (R_A + R_B) \times C_1$
|
||||
- Low time: $t_L = 0.693 \times R_B \times C_1$
|
||||
- Period: $T = t_H + t_L = 0.693 \times (R_A + 2R_B) \times C_1$
|
||||
- Frequency: $f = \frac{1.44}{(R_A + 2R_B) \times C_1}$
|
||||
- Duty Cycle: $D = \frac{R_A + R_B}{R_A + 2R_B}$
|
||||
|
||||
#### Figure 6. Capacitance and Resistance vs. Frequency
|
||||
|
||||
```mermaid
|
||||
%%{init: {'theme': 'base'}}%%
|
||||
xychart-beta
|
||||
title "Free Running Frequency vs Capacitance"
|
||||
x-axis "Frequency (Hz)" [0.1, 1, 10, 100, 1000, 10000, 100000]
|
||||
y-axis "Capacitance (μF)" 0.001 --> 100
|
||||
```
|
||||
|
||||
| (RA + 2RB) | C1 | Frequency |
|
||||
|:---|:---|:---|
|
||||
| 1.44 kΩ | 1 μF | 1 kHz |
|
||||
| 14.4 kΩ | 1 μF | 100 Hz |
|
||||
| 144 kΩ | 1 μF | 10 Hz |
|
||||
| 14.4 kΩ | 0.1 μF | 1 kHz |
|
||||
| 14.4 kΩ | 0.01 μF | 10 kHz |
|
||||
|
||||
#### Figure 7. Waveforms of Astable Operation
|
||||
|
||||
```
|
||||
Output ────┐ ┌─────┐ ┌─────┐ ┌────
|
||||
(Pin 3) └─────┘ └─────┘ └─────┘
|
||||
|←tL→|←─tH─→|←tL→|←─tH─→|
|
||||
|
||||
Threshold /\ /\ /\
|
||||
(Pin 6) ─────/ \──────/ \──────/ \──────
|
||||
Vcc/3 2Vcc/3
|
||||
|
||||
├────── T ──────┤
|
||||
T = tH + tL = 0.693(RA + 2RB)C1
|
||||
|
||||
Charging: C1 charges through RA + RB
|
||||
Discharging: C1 discharges through RB only
|
||||
```
|
||||
|
||||
**Typical Values:** RA = 1kΩ, RB = 1kΩ, C1 = 1μF, Vcc = 5V
|
||||
|
||||
An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high, resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:
|
||||
|
||||
#### Equation 1: Charging Circuit Equivalent
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
VCC["Vcc"] --> RA_RB["RA + RB"]
|
||||
RA_RB --> C1["C1<br/>Vc1(0-)=Vcc/3"]
|
||||
C1 --> GND["GND"]
|
||||
```
|
||||
|
||||
**Charging Equation:**
|
||||
$$C_1 \frac{dV_{C1}}{dt} = \frac{V_{CC} - V_{(0-)}}{R_A + R_B} \quad (1)$$
|
||||
|
||||
$$V_{C1}(0^+) = \frac{V_{CC}}{3} \quad (2)$$
|
||||
|
||||
$$V_{C1}(t) = V_{CC} \left[ 1 - \frac{2}{3} e^{-\frac{t}{(R_A + R_B)C_1}} \right] \quad (3)$$
|
||||
|
||||
Since the duration of the timer output high state (tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,
|
||||
|
||||
#### Equation 2: High Time Calculation
|
||||
|
||||
$$\frac{2}{3}V_{CC} = V_{CC} \left[ 1 - \frac{2}{3} e^{-\frac{t_H}{(R_A + R_B)C_1}} \right] \quad (4)$$
|
||||
|
||||
$$t_H = C_1(R_A + R_B) \ln 2 = 0.693(R_A + R_B)C_1 \quad (5)$$
|
||||
|
||||
The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:
|
||||
|
||||
#### Equation 3: Discharging Circuit Equivalent
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
C1["C1<br/>Vc1(0-)=2Vcc/3"] --> RB["RB"]
|
||||
RB --> RD["RD<br/>(discharge Tr.)"]
|
||||
RD --> GND["GND"]
|
||||
```
|
||||
|
||||
**Discharging Equation:**
|
||||
$$C_1 \frac{dV_{C1}}{dt} + \frac{1}{R_A + R_B} V_{C1} = 0 \quad (6)$$
|
||||
|
||||
$$V_{C1}(t) = \frac{2}{3} V_{CC} e^{-\frac{t}{(R_A + R_B)C_1}} \quad (7)$$
|
||||
|
||||
Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,
|
||||
|
||||
#### Equation 4: Low Time Calculation
|
||||
|
||||
$$\frac{1}{3}V_{CC} = \frac{2}{3}V_{CC} e^{-\frac{t_L}{(R_B + R_D)C_1}} \quad (8)$$
|
||||
|
||||
$$t_L = C_1(R_B + R_D) \ln 2 = 0.693(R_A + R_B)C_1 \quad (9)$$
|
||||
|
||||
Since RD is normally RB>>RD although related to the size of discharging Tr., tL=0.693RBC1 (10)
|
||||
Consequently, if the timer operates in astable, the period is the same with 'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.
|
||||
|
||||
#### Equation 5: Frequency Formula
|
||||
|
||||
$$f = \frac{1}{T} = \frac{1.44}{(R_A + 2R_B)C_1} \quad (11)$$
|
||||
|
||||
### 3. Frequency divider
|
||||
|
||||
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure
|
||||
8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
|
||||
|
||||
#### Figure 8. Waveforms of Frequency Divider Operation
|
||||
|
||||
```
|
||||
Trigger ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
|
||||
(Input) └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
|
||||
1 2 3 1 2 3 1 2 3
|
||||
|
||||
Output ─┐ ┌──┐ ┌──┐ ┌──────
|
||||
(÷3) └────────┘ └────────┘ └────────┘
|
||||
|← skip →| |← skip →| |← skip →|
|
||||
2,3 2,3 2,3
|
||||
|
||||
Threshold /‾‾‾‾\ /‾‾‾‾\ /‾‾‾‾\
|
||||
(Vc1) ─────/ \──────/ \──────/
|
||||
|
||||
RA = 9.1kΩ, RB = 1kΩ, C1 = 0.01μF, Vcc = 5V
|
||||
|
||||
⚙️ Divide-by-N: Set timing so output ignores (N-1) trigger pulses
|
||||
```
|
||||
|
||||
### 4. Pulse Width Modulation
|
||||
|
||||
The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit. When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.
|
||||
|
||||
#### Figure 9. Circuit for Pulse Width Modulation
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
subgraph CIRCUIT["PWM Configuration"]
|
||||
VCC["+Vcc"]
|
||||
|
||||
subgraph TIMER["555 Timer"]
|
||||
P4["4<br/>RESET"]
|
||||
P8["8<br/>Vcc"]
|
||||
P7["7<br/>DISCH"]
|
||||
P2["2<br/>TRIG"]
|
||||
P6["6<br/>THRES"]
|
||||
P3["3<br/>OUT"]
|
||||
P5["5<br/>CONT"]
|
||||
P1["1<br/>GND"]
|
||||
end
|
||||
|
||||
RA["RA"]
|
||||
C1["C1"]
|
||||
C2["C2"]
|
||||
GND["GND"]
|
||||
end
|
||||
|
||||
VCC --> P4
|
||||
VCC --> P8
|
||||
VCC --> RA
|
||||
RA --> P7
|
||||
P7 --> P6
|
||||
P6 --> C1
|
||||
C1 --> GND
|
||||
|
||||
TRIG_IN["Trigger<br/>Pulse Train"] --> P2
|
||||
MOD["Modulation<br/>Signal"] --> P5
|
||||
P5 --> C2
|
||||
C2 --> GND
|
||||
|
||||
P3 --> OUTPUT["PWM<br/>Output"]
|
||||
P1 --> GND
|
||||
|
||||
style VCC fill:#f00,color:#fff
|
||||
style GND fill:#000,color:#fff
|
||||
style TRIG_IN fill:#f96
|
||||
style MOD fill:#ff6
|
||||
style OUTPUT fill:#6f6
|
||||
```
|
||||
|
||||
#### Figure 10. Waveforms of Pulse Width Modulation
|
||||
|
||||
```
|
||||
Control ╭──────╮ ╭──────╮ ╭──────╮
|
||||
(Pin 5) │ │ │ │ │ │
|
||||
───╯ ╰──────╯ ╰──────╯ ╰───
|
||||
|← Modulation Signal (e.g., Sine) →|
|
||||
|
||||
Trigger ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
|
||||
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
|
||||
|
||||
Output ─┐ ┌─┐ ┌───┐ ┌─┐ ┌─┐ ┌───┐ ┌─
|
||||
(PWM) └──┘ └───┘ └───┘ └──┘ └───┘ └───┘
|
||||
|←w1→|←w2─→|←w3──→|
|
||||
|
||||
Pulse width varies with control voltage:
|
||||
- Higher control voltage → Longer pulse width
|
||||
- Lower control voltage → Shorter pulse width
|
||||
|
||||
RA = 3.9kΩ, RB = 1kΩ, RL = 1kΩ, C1 = 0.01μF, Vcc = 5V
|
||||
```
|
||||
|
||||
### 5. Pulse Position Modulation
|
||||
|
||||
If the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.
|
||||
|
||||
#### Figure 11. Circuit for Pulse Position Modulation
|
||||
|
||||
```mermaid
|
||||
flowchart LR
|
||||
subgraph CIRCUIT["PPM Configuration"]
|
||||
VCC["+Vcc"]
|
||||
|
||||
subgraph TIMER["555 Timer"]
|
||||
P4["4<br/>RESET"]
|
||||
P8["8<br/>Vcc"]
|
||||
P7["7<br/>DISCH"]
|
||||
P2["2<br/>TRIG"]
|
||||
P6["6<br/>THRES"]
|
||||
P3["3<br/>OUT"]
|
||||
P5["5<br/>CONT"]
|
||||
P1["1<br/>GND"]
|
||||
end
|
||||
|
||||
RA["RA"]
|
||||
RB["RB"]
|
||||
C1["C1"]
|
||||
GND["GND"]
|
||||
end
|
||||
|
||||
VCC --> P4
|
||||
VCC --> P8
|
||||
VCC --> RA
|
||||
RA --> P7
|
||||
P7 --> RB
|
||||
RB --> P6
|
||||
RB --> P2
|
||||
P6 --> C1
|
||||
C1 --> GND
|
||||
|
||||
MOD["Modulation<br/>Signal"] --> P5
|
||||
|
||||
P3 --> OUTPUT["PPM<br/>Output"]
|
||||
P1 --> GND
|
||||
|
||||
style VCC fill:#f00,color:#fff
|
||||
style GND fill:#000,color:#fff
|
||||
style MOD fill:#ff6
|
||||
style OUTPUT fill:#6f6
|
||||
```
|
||||
|
||||
#### Figure 12. Waveforms of Pulse Position Modulation
|
||||
|
||||
```
|
||||
Control ╭────────────╮ ╭────────────╮
|
||||
(Pin 5) │ │ │ │
|
||||
───╯ ╰──────────╯ ╰───
|
||||
Modulation Signal (Sine Wave)
|
||||
|
||||
Threshold /\ /\ /\ /\ /\
|
||||
(Pin 6) ────/ \──/ \────/ \────/ \──/ \────
|
||||
|
||||
Output ─┐ ┌─┐ ┌──┐ ┌────┐ ┌──┐ ┌─┐ ┌─
|
||||
(PPM) └─┘ └──┘ └────┘ └────┘ └──┘ └─┘
|
||||
|←t1→|←t2─→|←─t3──→|←t4─→|←t5→|
|
||||
|
||||
Pulse spacing varies with control voltage:
|
||||
- Higher control voltage → Longer period
|
||||
- Lower control voltage → Shorter period
|
||||
|
||||
RA = 1kΩ, RB = 1kΩ, C1 = 1nF, Vcc = 5V
|
||||
```
|
||||
|
||||
### 6. Linear Ramp
|
||||
|
||||
When the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.
|
||||
|
||||
#### Figure 13. Circuit for Linear Ramp
|
||||
|
||||
```mermaid
|
||||
flowchart TB
|
||||
subgraph CIRCUIT["Linear Ramp Generator"]
|
||||
VCC["+Vcc"]
|
||||
|
||||
subgraph CURRENT_SOURCE["Constant Current Source"]
|
||||
RE["RE"]
|
||||
Q1["Q1<br/>PNP"]
|
||||
R1["R1"]
|
||||
R2["R2"]
|
||||
end
|
||||
|
||||
subgraph TIMER["555 Timer"]
|
||||
P4["4<br/>RESET"]
|
||||
P8["8<br/>Vcc"]
|
||||
P7["7<br/>DISCH"]
|
||||
P2["2<br/>TRIG"]
|
||||
P6["6<br/>THRES"]
|
||||
P3["3<br/>OUT"]
|
||||
P5["5<br/>CONT"]
|
||||
P1["1<br/>GND"]
|
||||
end
|
||||
|
||||
C1["C1"]
|
||||
C2["C2"]
|
||||
GND["GND"]
|
||||
end
|
||||
|
||||
VCC --> P4
|
||||
VCC --> P8
|
||||
VCC --> RE
|
||||
VCC --> R1
|
||||
|
||||
RE --> Q1
|
||||
R1 --> Q1
|
||||
Q1 --> R2
|
||||
R2 --> GND
|
||||
|
||||
Q1 -->|Ic| P7
|
||||
P7 --> P6
|
||||
P6 --> C1
|
||||
C1 --> GND
|
||||
|
||||
TRIG_IN["Trigger"] --> P2
|
||||
|
||||
P3 --> OUTPUT["Output"]
|
||||
P5 --> C2
|
||||
C2 --> GND
|
||||
P1 --> GND
|
||||
|
||||
style VCC fill:#f00,color:#fff
|
||||
style GND fill:#000,color:#fff
|
||||
style Q1 fill:#fcf,color:#000
|
||||
style OUTPUT fill:#6f6
|
||||
```
|
||||
|
||||
#### Figure 14. Waveforms of Linear Ramp
|
||||
|
||||
```
|
||||
Trigger ─────┐ ┌───────────────────────────
|
||||
(Pin 2) └─────┘
|
||||
↓ Trigger pulse
|
||||
|
||||
Output ─────────┐ ┌───────────────
|
||||
(Pin 3) └──────────────┘
|
||||
|←──── td ────→|
|
||||
|
||||
Threshold ╱ Linear ramp (not exponential)
|
||||
(Pin 6) ─────╱
|
||||
0V ↗
|
||||
Vcc/3 2Vcc/3
|
||||
|
||||
Linear ramp: Vc1 = (Ic/C1) × t
|
||||
Slope S = Ic/C1
|
||||
|
||||
R1 = 47kΩ, R2 = 100kΩ, RE = 2.7kΩ, RL = 1kΩ, C1 = 0.01μF, Vcc = 5V
|
||||
```
|
||||
|
||||
In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.
|
||||
|
||||
#### Equation 6: Current Source Calculation
|
||||
|
||||
$$I_C = \frac{V_{CC} - V_E}{R_E} \quad (12)$$
|
||||
|
||||
Here, VE is:
|
||||
|
||||
$$V_E = V_{BE} + \frac{R_2}{R_1 + R_2} V_{CC} \quad (13)$$
|
||||
|
||||
For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V, VE=0.7V+10V=10.7V Ic=(15-10.7)/20k=0.215mA
|
||||
|
||||
When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows:
|
||||
|
||||
#### Equation 7: Ramp Slope
|
||||
|
||||
$$S = \frac{V_{P-P}}{T} \quad (14)$$
|
||||
|
||||
Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:
|
||||
|
||||
```
|
||||
V = Q/C (15)
|
||||
```
|
||||
|
||||
The above equation divided on both sides by T gives us
|
||||
|
||||
#### Equation 8: Simplified Ramp Slope
|
||||
|
||||
$$\frac{V}{T} = \frac{Q/T}{C} \quad (16)$$
|
||||
|
||||
and may be simplified into the following equation.
|
||||
|
||||
```
|
||||
S = I/C (17)
|
||||
```
|
||||
|
||||
In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02μF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022μ = 9.77V/ms.
|
||||
|
||||
# Mechanical Dimensions
|
||||
|
||||
## Package
|
||||
|
||||
### 8-DIP (Dual In-line Package)
|
||||
|
||||
```
|
||||
┌─────────────────────────────────────┐
|
||||
│ ● │
|
||||
│ #1 #8 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #2 #7 │
|
||||
│ ┌──┐ 555 TIMER ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #3 #6 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #4 #5 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
└─────────────────────────────────────┘
|
||||
```
|
||||
|
||||
**8-DIP Dimensions (in millimeters):**
|
||||
|
||||
| Parameter | Min | Nom | Max |
|
||||
|:---|:---:|:---:|:---:|
|
||||
| Package Length | - | 9.60 | - |
|
||||
| Package Width | 6.20 | 6.40 | 6.60 |
|
||||
| Package Height | - | 5.08 | - |
|
||||
| Lead Pitch | - | 2.54 | - |
|
||||
| Lead Width | 0.36 | 0.46 | 0.56 |
|
||||
| Lead Thickness | - | 0.33 | - |
|
||||
| Lead Length | 2.92 | 3.30 | 3.68 |
|
||||
| Standoff | 0.51 | - | - |
|
||||
|
||||
```
|
||||
6.40 ± 0.20
|
||||
┌────────────────┐
|
||||
│ │
|
||||
┌────┤ ├────┐
|
||||
│ │ │ │ 9.60
|
||||
│ │ │ │ MAX
|
||||
│ │ │ │
|
||||
└────┤ ├────┘
|
||||
│ │
|
||||
└────────────────┘
|
||||
↕ 2.54 (pin pitch)
|
||||
|
||||
Side View:
|
||||
┌────────────────┐
|
||||
5.08 │ │
|
||||
MAX └──┬──┬──┬──┬──┬─┘
|
||||
│ │ │ │ │ 3.30 ± 0.30
|
||||
│ │ │ │ │ (lead length)
|
||||
═══╧══╧══╧══╧══╧═══
|
||||
↕ 0.33 MIN
|
||||
```
|
||||
|
||||
### 8-SOP (Small Outline Package)
|
||||
|
||||
```
|
||||
┌───────────────────────────────┐
|
||||
│ ● │
|
||||
│ #1 #8 │
|
||||
│ ─┐ ┌─ │
|
||||
│ │ │ │
|
||||
├───┴───────────────────────┴───┤
|
||||
│ 555 TIMER │
|
||||
├───┬───────────────────────┬───┤
|
||||
│ │ │ │
|
||||
│ ─┘ └─ │
|
||||
│ #4 #5 │
|
||||
└───────────────────────────────┘
|
||||
```
|
||||
|
||||
**8-SOP Dimensions (in millimeters):**
|
||||
|
||||
| Parameter | Min | Nom | Max |
|
||||
|:---|:---:|:---:|:---:|
|
||||
| Package Length | 4.72 | 4.92 | 5.12 |
|
||||
| Package Width | 5.70 | 6.00 | 6.30 |
|
||||
| Package Height | - | 1.55 | 1.75 |
|
||||
| Lead Pitch | - | 1.27 | - |
|
||||
| Lead Width | 0.31 | 0.41 | 0.51 |
|
||||
| Lead Length (toe) | 0.40 | 0.80 | 1.27 |
|
||||
| Standoff | 0.05 | 0.15 | 0.25 |
|
||||
| Overall Width (with leads) | - | 6.00 | - |
|
||||
|
||||
```
|
||||
6.00 ± 0.30
|
||||
┌────────────────┐
|
||||
─┐ │ │ ┌─
|
||||
│ │ │ │ 4.92 ± 0.20
|
||||
─┘ │ │ └─
|
||||
└────────────────┘
|
||||
↕ 1.27 (pin pitch)
|
||||
|
||||
Side View:
|
||||
1.55 ± 0.20
|
||||
┌────────────────┐
|
||||
MAX │ │
|
||||
└──┬──┬──┬──┬──┬─┘
|
||||
└──┴──┴──┴──┴── 0.10~0.25 standoff
|
||||
```
|
||||
|
||||
## Pin Assignment Summary
|
||||
|
||||
| Pin | Symbol | 8-DIP | 8-SOP | Description |
|
||||
|:---:|:---:|:---:|:---:|:---|
|
||||
| 1 | GND | ● | ● | Ground (0V) |
|
||||
| 2 | TRIG | ● | ● | Trigger input |
|
||||
| 3 | OUT | ● | ● | Output |
|
||||
| 4 | RESET | ● | ● | Reset (active low) |
|
||||
| 5 | CONT | ● | ● | Control voltage |
|
||||
| 6 | THRES | ● | ● | Threshold input |
|
||||
| 7 | DISCH | ● | ● | Discharge |
|
||||
| 8 | Vcc | ● | ● | Supply voltage |
|
||||
221
skills/legacy-circuit-mockups/references/6502.md
Normal file
221
skills/legacy-circuit-mockups/references/6502.md
Normal file
@@ -0,0 +1,221 @@
|
||||
# MOS Technology 6502 Microprocessor Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **MOS Technology 6502** is an 8-bit microprocessor introduced in 1975. It is notable for its low cost, efficient instruction set, and widespread use in early personal computers and game consoles, including the Apple II, Commodore 64, Atari 2600, NES (Ricoh 2A03 variant), and BBC Micro.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| ------------- | ------------------------ |
|
||||
| Data width | 8-bit |
|
||||
| Address width | 16-bit |
|
||||
| Address space | 64 KB (0x0000–0xFFFF) |
|
||||
| Registers | A, X, Y, SP, PC, P |
|
||||
| Endianness | Little-endian |
|
||||
| Clock speed | ~1–3 MHz (original NMOS) |
|
||||
| Technology | NMOS |
|
||||
|
||||
---
|
||||
|
||||
## 3. Programmer-Visible Registers
|
||||
|
||||
### 3.1 Accumulator (A)
|
||||
|
||||
* 8-bit register
|
||||
* Used for arithmetic, logic, and data transfer operations
|
||||
|
||||
### 3.2 Index Registers (X, Y)
|
||||
|
||||
* 8-bit registers
|
||||
* Used for indexing memory, counters, and offsets
|
||||
|
||||
### 3.3 Stack Pointer (SP)
|
||||
|
||||
* 8-bit register
|
||||
* Points to the current stack location
|
||||
* Stack resides in page `$0100–$01FF`
|
||||
|
||||
### 3.4 Program Counter (PC)
|
||||
|
||||
* 16-bit register
|
||||
* Holds address of next instruction
|
||||
|
||||
### 3.5 Processor Status Register (P)
|
||||
|
||||
| Bit | Name | Description |
|
||||
| --: | ---- | ----------------------------- |
|
||||
| 7 | N | Negative |
|
||||
| 6 | V | Overflow |
|
||||
| 5 | – | Unused (always set in pushes) |
|
||||
| 4 | B | Break |
|
||||
| 3 | D | Decimal Mode |
|
||||
| 2 | I | Interrupt Disable |
|
||||
| 1 | Z | Zero |
|
||||
| 0 | C | Carry |
|
||||
|
||||
---
|
||||
|
||||
## 4. Memory Map Conventions
|
||||
|
||||
| Address Range | Usage |
|
||||
| ------------- | -------------------- |
|
||||
| `$0000–$00FF` | Zero Page |
|
||||
| `$0100–$01FF` | Hardware Stack |
|
||||
| `$0200–$FFFF` | Program / Data / I/O |
|
||||
|
||||
### 4.1 Interrupt Vectors
|
||||
|
||||
| Vector | Address | Description |
|
||||
| ------- | ------------- | ---------------------- |
|
||||
| NMI | `$FFFA–$FFFB` | Non-maskable interrupt |
|
||||
| RESET | `$FFFC–$FFFD` | Reset vector |
|
||||
| IRQ/BRK | `$FFFE–$FFFF` | Interrupt request |
|
||||
|
||||
---
|
||||
|
||||
## 5. Addressing Modes
|
||||
|
||||
| Mode | Syntax | Description |
|
||||
| ---------------- | ------------- | ----------------------- |
|
||||
| Implied | `CLC` | Operand implied |
|
||||
| Accumulator | `ASL A` | Operates on accumulator |
|
||||
| Immediate | `LDA #$10` | Constant value |
|
||||
| Zero Page | `LDA $20` | Zero-page address |
|
||||
| Zero Page,X | `LDA $20,X` | Zero-page indexed |
|
||||
| Zero Page,Y | `LDX $20,Y` | Zero-page indexed |
|
||||
| Absolute | `LDA $1234` | Full 16-bit address |
|
||||
| Absolute,X | `LDA $1234,X` | Indexed absolute |
|
||||
| Absolute,Y | `LDA $1234,Y` | Indexed absolute |
|
||||
| Indirect | `JMP ($1234)` | Pointer-based jump |
|
||||
| Indexed Indirect | `LDA ($20,X)` | X-indexed pointer |
|
||||
| Indirect Indexed | `LDA ($20),Y` | Y-indexed pointer |
|
||||
| Relative | `BEQ label` | Branch offset |
|
||||
|
||||
---
|
||||
|
||||
## 6. Instruction Set Summary
|
||||
|
||||
### 6.1 Load / Store
|
||||
|
||||
* `LDA`, `LDX`, `LDY`
|
||||
* `STA`, `STX`, `STY`
|
||||
|
||||
### 6.2 Register Transfers
|
||||
|
||||
* `TAX`, `TAY`, `TXA`, `TYA`, `TSX`, `TXS`
|
||||
|
||||
### 6.3 Stack Operations
|
||||
|
||||
* `PHA`, `PLA`, `PHP`, `PLP`
|
||||
|
||||
### 6.4 Arithmetic
|
||||
|
||||
* `ADC` – Add with Carry
|
||||
* `SBC` – Subtract with Carry
|
||||
|
||||
### 6.5 Logical
|
||||
|
||||
* `AND`, `ORA`, `EOR`
|
||||
|
||||
### 6.6 Shifts and Rotates
|
||||
|
||||
* `ASL`, `LSR`, `ROL`, `ROR`
|
||||
|
||||
### 6.7 Increment / Decrement
|
||||
|
||||
* `INC`, `INX`, `INY`
|
||||
* `DEC`, `DEX`, `DEY`
|
||||
|
||||
### 6.8 Comparisons
|
||||
|
||||
* `CMP`, `CPX`, `CPY`
|
||||
|
||||
### 6.9 Branching
|
||||
|
||||
* `BEQ`, `BNE`, `BMI`, `BPL`, `BCS`, `BCC`, `BVS`, `BVC`
|
||||
|
||||
### 6.10 Jumps & Subroutines
|
||||
|
||||
* `JMP`, `JSR`, `RTS`, `RTI`
|
||||
|
||||
### 6.11 Status Flag Control
|
||||
|
||||
* `CLC`, `SEC`, `CLI`, `SEI`, `CLV`, `CLD`, `SED`
|
||||
|
||||
### 6.12 System Control
|
||||
|
||||
* `BRK`, `NOP`
|
||||
|
||||
---
|
||||
|
||||
## 7. Cycle Timing (General)
|
||||
|
||||
* Most instructions execute in **2–7 cycles**
|
||||
* Additional cycles may be added for:
|
||||
|
||||
* Page boundary crossings
|
||||
* Taken branches
|
||||
|
||||
---
|
||||
|
||||
## 8. Decimal Mode
|
||||
|
||||
When the **D flag** is set:
|
||||
|
||||
* `ADC` and `SBC` operate using **BCD arithmetic**
|
||||
* Only valid on NMOS 6502 (behavior varies on CMOS derivatives)
|
||||
|
||||
---
|
||||
|
||||
## 9. Known Hardware Quirks
|
||||
|
||||
* `JMP (addr)` indirect bug: page boundary wraparound
|
||||
|
||||
* Example: `JMP ($10FF)` reads from `$10FF` and `$1000`
|
||||
* No dedicated multiply or divide instructions
|
||||
* Stack is fixed to page `$01xx`
|
||||
|
||||
---
|
||||
|
||||
## 10. Variants and Derivatives
|
||||
|
||||
| Variant | Notes |
|
||||
| ------- | ----------------------------------- |
|
||||
| 6502 | Original NMOS |
|
||||
| 65C02 | CMOS, fixes bugs, adds instructions |
|
||||
| 2A03 | NES variant, decimal mode disabled |
|
||||
| 6510 | Adds I/O port (Commodore 64) |
|
||||
|
||||
---
|
||||
|
||||
## 11. Example Code
|
||||
|
||||
```asm
|
||||
LDX #$00
|
||||
loop: INX
|
||||
TXA
|
||||
STA $0200,X
|
||||
CPX #$10
|
||||
BNE loop
|
||||
BRK
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 12. References
|
||||
|
||||
* <https://syncopate.us/books/Synertek6502ProgrammingManual.html>
|
||||
* <https://en.wikipedia.org/wiki/MOS_Technology_6502>
|
||||
* <https://web.archive.org/web/20061114024257/http://www.westerndesigncenter.com/wdc/documentation/Programmanual.pdf>
|
||||
* Tutorial excerpts from <https://wilsonminesco.com/6502primer/>
|
||||
* <https://wilsonminesco.com/6502primer/LogicFamilies.html>
|
||||
* <https://wilsonminesco.com/6502primer/ClkGen.html>
|
||||
* <https://wilsonminesco.com/6502primer/RSTreqs.html>
|
||||
* <https://wilsonminesco.com/6502primer/displays.html>
|
||||
* <https://wilsonminesco.com/6502primer/debug.html>
|
||||
* <https://wilsonminesco.com/6502primer/potpourri.html>
|
||||
|
||||
---
|
||||
211
skills/legacy-circuit-mockups/references/6522.md
Normal file
211
skills/legacy-circuit-mockups/references/6522.md
Normal file
@@ -0,0 +1,211 @@
|
||||
# MOS Technology 6522 Versatile Interface Adapter (VIA)
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **MOS Technology 6522 VIA** is a general-purpose I/O controller designed to interface the 6502 family of microprocessors with external peripherals. Introduced in the mid-1970s, it provides parallel I/O ports, timers, shift register support, and interrupt handling. The 6522 is widely used in systems such as the Commodore PET, VIC-20, Apple II, BBC Micro, and many 6502-based embedded designs.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| -------------- | -------------------------------- |
|
||||
| Data width | 8-bit |
|
||||
| Addressing | Memory-mapped I/O |
|
||||
| Registers | 16 (4-bit register select) |
|
||||
| I/O ports | Two 8-bit ports (Port A, Port B) |
|
||||
| Timers | Two 16-bit timers |
|
||||
| Shift register | 8-bit serial I/O |
|
||||
| Interrupts | Maskable, multiple sources |
|
||||
| Clock | System clock (φ2) |
|
||||
|
||||
---
|
||||
|
||||
## 3. Pin Functions (Logical)
|
||||
|
||||
### 3.1 Port A (PA0-PA7)
|
||||
|
||||
* 8-bit bidirectional parallel I/O
|
||||
* Handshake support via CA1 / CA2
|
||||
|
||||
### 3.2 Port B (PB0-PB7)
|
||||
|
||||
* 8-bit bidirectional parallel I/O
|
||||
* Handshake support via CB1 / CB2
|
||||
* PB6 and PB7 may be controlled by Timer 1
|
||||
|
||||
### 3.3 Control Pins
|
||||
|
||||
| Pin | Description |
|
||||
| --------- | ------------------------------------- |
|
||||
| CA1 / CB1 | Interrupt-capable control inputs |
|
||||
| CA2 / CB2 | Handshake / pulse / interrupt pins |
|
||||
| IRQ | Interrupt request output (active low) |
|
||||
| RESET | Reset input |
|
||||
|
||||
---
|
||||
|
||||
## 4. Register Map
|
||||
|
||||
Registers are selected using 4 address lines (RS0-RS3). The base address is system-defined.
|
||||
|
||||
| Offset | Register | Description |
|
||||
| -----: | --------- | ------------------------------------ |
|
||||
| $0 | ORB | Output Register B |
|
||||
| $1 | ORA / IRB | Output Register A / Input Register B |
|
||||
| $2 | DDRB | Data Direction Register B |
|
||||
| $3 | DDRA | Data Direction Register A |
|
||||
| $4 | T1C-L | Timer 1 Counter Low |
|
||||
| $5 | T1C-H | Timer 1 Counter High |
|
||||
| $6 | T1L-L | Timer 1 Latch Low |
|
||||
| $7 | T1L-H | Timer 1 Latch High |
|
||||
| $8 | T2C-L | Timer 2 Counter Low |
|
||||
| $9 | T2C-H | Timer 2 Counter High |
|
||||
| $A | SR | Shift Register |
|
||||
| $B | ACR | Auxiliary Control Register |
|
||||
| $C | PCR | Peripheral Control Register |
|
||||
| $D | IFR | Interrupt Flag Register |
|
||||
| $E | IER | Interrupt Enable Register |
|
||||
| $F | ORA / IRA | Output Register A / Input Register A |
|
||||
|
||||
---
|
||||
|
||||
## 5. Data Direction Registers (DDRA / DDRB)
|
||||
|
||||
Each bit controls the direction of its corresponding port pin:
|
||||
|
||||
* `0` = Input
|
||||
* `1` = Output
|
||||
|
||||
```text
|
||||
DDRB bit = 1 PBx is output
|
||||
DDRB bit = 0 PBx is input
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 6. Timers
|
||||
|
||||
### 6.1 Timer 1 (T1)
|
||||
|
||||
* 16-bit down counter
|
||||
* Can operate in one-shot or free-running mode
|
||||
* Can toggle PB7 on timeout
|
||||
* Generates interrupts
|
||||
|
||||
### 6.2 Timer 2 (T2)
|
||||
|
||||
* 16-bit down counter
|
||||
* Supports pulse counting on PB6
|
||||
* One-shot operation only
|
||||
|
||||
---
|
||||
|
||||
## 7. Shift Register (SR)
|
||||
|
||||
* 8-bit shift register
|
||||
* Can shift data in or out
|
||||
* Clock source selectable via ACR
|
||||
* Often used for serial communication or keyboard scanning
|
||||
|
||||
---
|
||||
|
||||
## 8. Control Registers
|
||||
|
||||
### 8.1 Auxiliary Control Register (ACR)
|
||||
|
||||
| Bit | Function |
|
||||
| --: | ---------------------------------- |
|
||||
| 7 | Timer 1 control (PB7 output) |
|
||||
| 6 | Timer 1 mode (free-run / one-shot) |
|
||||
| 5 | Timer 2 control |
|
||||
| 4 | Shift register mode |
|
||||
| 3 | Shift register clock source |
|
||||
| 2 | Port B latching |
|
||||
| 1 | Port A latching |
|
||||
| 0 | Unused |
|
||||
|
||||
### 8.2 Peripheral Control Register (PCR)
|
||||
|
||||
Controls CA1, CA2, CB1, CB2 behavior:
|
||||
|
||||
* Input/output mode
|
||||
* Active edge selection
|
||||
* Pulse or handshake modes
|
||||
|
||||
---
|
||||
|
||||
## 9. Interrupt System
|
||||
|
||||
### 9.1 Interrupt Flag Register (IFR)
|
||||
|
||||
| Bit | Source |
|
||||
| --: | ---------------------------------- |
|
||||
| 7 | IRQ status (any enabled interrupt) |
|
||||
| 6 | Timer 1 |
|
||||
| 5 | Timer 2 |
|
||||
| 4 | CB1 |
|
||||
| 3 | CB2 |
|
||||
| 2 | Shift Register |
|
||||
| 1 | CA1 |
|
||||
| 0 | CA2 |
|
||||
|
||||
### 9.2 Interrupt Enable Register (IER)
|
||||
|
||||
* Bit 7 determines set/clear mode:
|
||||
|
||||
* `1` = set bits
|
||||
* `0` = clear bits
|
||||
|
||||
```text
|
||||
Write $80 | mask enable interrupts
|
||||
Write $00 | mask disable interrupts
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 10. Reset Behavior
|
||||
|
||||
On RESET:
|
||||
|
||||
* All DDR bits cleared (ports default to input)
|
||||
* Timers stopped
|
||||
* Shift register disabled
|
||||
* Interrupts disabled
|
||||
|
||||
---
|
||||
|
||||
## 11. Timing Notes
|
||||
|
||||
* VIA registers are accessed synchronously with φ2
|
||||
* Timer counters decrement once per φ2 cycle
|
||||
* Some operations have side effects when reading/writing registers
|
||||
|
||||
---
|
||||
|
||||
## 12. Common Use Cases
|
||||
|
||||
* Keyboard and joystick interfaces
|
||||
* Parallel printer interfaces
|
||||
* Timers and event counting
|
||||
* Simple serial communications
|
||||
* General-purpose GPIO expansion
|
||||
|
||||
---
|
||||
|
||||
## 13. Variants and Related Chips
|
||||
|
||||
| Chip | Notes |
|
||||
| ----- | ----------------------------- |
|
||||
| 6522 | Original NMOS VIA |
|
||||
| 65C22 | CMOS VIA, faster, lower power |
|
||||
| 6520 | Earlier PIA (simpler) |
|
||||
|
||||
---
|
||||
|
||||
## 14. References
|
||||
|
||||
* <https://en.wikipedia.org/wiki/MOS_Technology_6522>
|
||||
* <https://grokipedia.com/page/MOS_Technology_6522>
|
||||
|
||||
---
|
||||
177
skills/legacy-circuit-mockups/references/6C62256.md
Normal file
177
skills/legacy-circuit-mockups/references/6C62256.md
Normal file
@@ -0,0 +1,177 @@
|
||||
# AS6C62256 32K x 8 Low-Power CMOS SRAM Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **AS6C62256** is a **256 Kbit (32K x 8)** low-power CMOS static random-access memory (SRAM) manufactured by Alliance Memory (and second-sourced by others). It is fully compatible with common 28-pin SRAM pinouts and is widely used in **6502**, **Z80**, and other 8-bit microprocessor systems for read/write memory.
|
||||
|
||||
The device offers fast access times, simple control logic, and very low standby power consumption.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| ----------------- | --------------------------------- |
|
||||
| Memory size | 256 Kbits (32 KB) |
|
||||
| Organization | 32,768 x 8 bits |
|
||||
| Data bus | 8-bit |
|
||||
| Address bus | 15-bit (A0-A14) |
|
||||
| Technology | CMOS SRAM |
|
||||
| Access time | 55 ns / 70 ns (variant dependent) |
|
||||
| Operating voltage | 5 V ± 10% |
|
||||
| Standby current | < 1 µA (typical) |
|
||||
| Package types | DIP-28, SOJ-28, TSOP-28 |
|
||||
|
||||
---
|
||||
|
||||
## 3. Pin Configuration (Logical)
|
||||
|
||||
### 3.1 Address Pins (A0-A14)
|
||||
|
||||
* Select one of 32,768 memory locations
|
||||
* Address must be stable during read or write cycle
|
||||
|
||||
### 3.2 Data Pins (I/O0-I/O7)
|
||||
|
||||
* Bidirectional tri-state data bus
|
||||
* High-impedance when not enabled
|
||||
|
||||
### 3.3 Control Pins
|
||||
|
||||
| Pin | Description |
|
||||
| --- | -------------------------- |
|
||||
| CE# | Chip Enable (active low) |
|
||||
| OE# | Output Enable (active low) |
|
||||
| WE# | Write Enable (active low) |
|
||||
| VCC | +5 V power supply |
|
||||
| GND | Ground |
|
||||
|
||||
---
|
||||
|
||||
## 4. Memory Organization
|
||||
|
||||
* Linear address space from `$0000` to `$7FFF`
|
||||
* Each address corresponds to one byte (8 bits)
|
||||
|
||||
```text
|
||||
Address range: 0000h - 7FFFh
|
||||
Data width: 8 bits
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 5. Read Operation
|
||||
|
||||
### 5.1 Read Cycle Conditions
|
||||
|
||||
| Signal | State |
|
||||
| ------ | ----- |
|
||||
| CE? | LOW |
|
||||
| OE? | LOW |
|
||||
| WE? | HIGH |
|
||||
|
||||
* Data becomes valid after access time (tAA)
|
||||
* Outputs remain valid while CE? and OE? are LOW
|
||||
* Outputs are high-impedance when CE? or OE? is HIGH
|
||||
|
||||
---
|
||||
|
||||
## 6. Write Operation
|
||||
|
||||
### 6.1 Write Cycle Conditions
|
||||
|
||||
| Signal | State |
|
||||
| ------ | ----------- |
|
||||
| CE? | LOW |
|
||||
| OE? | HIGH or LOW |
|
||||
| WE? | LOW pulse |
|
||||
|
||||
* Data is written on the rising edge of WE? or CE?
|
||||
* Address and data must be stable during write window
|
||||
* No internal write delay (true SRAM behavior)
|
||||
|
||||
---
|
||||
|
||||
## 7. Timing Notes (Summary)
|
||||
|
||||
| Parameter | Typical |
|
||||
| -------------------- | -------- |
|
||||
| Address access (tAA) | 55-70 ns |
|
||||
| CE? access (tACE) | 55-70 ns |
|
||||
| OE? access (tOE) | 25-35 ns |
|
||||
| Write cycle time | ≥ 55 ns |
|
||||
|
||||
---
|
||||
|
||||
## 8. Power Modes
|
||||
|
||||
### 8.1 Active Mode
|
||||
|
||||
* CE? = LOW
|
||||
* Normal read/write operation
|
||||
|
||||
### 8.2 Standby Mode
|
||||
|
||||
* CE? = HIGH
|
||||
* Data retained
|
||||
* Very low power consumption
|
||||
|
||||
---
|
||||
|
||||
## 9. Reset and Power-Up Behavior
|
||||
|
||||
* No reset pin required
|
||||
* Data is undefined at power-up
|
||||
* Memory contents preserved only while VCC is present
|
||||
|
||||
---
|
||||
|
||||
## 10. Typical System Integration (6502 Example)
|
||||
|
||||
```text
|
||||
Mapped at: $0000 - $7FFF
|
||||
CE? decoded address
|
||||
OE? R/W?
|
||||
WE? inverted R/W?
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 11. Absolute Maximum Ratings (Summary)
|
||||
|
||||
| Parameter | Rating |
|
||||
| ------------- | --------------------- |
|
||||
| VCC | -0.5 V to +6.5 V |
|
||||
| Input voltage | -0.5 V to VCC + 0.5 V |
|
||||
| Storage temp | -65 °C to +150 °C |
|
||||
|
||||
---
|
||||
|
||||
## 12. Compatible and Equivalent Devices
|
||||
|
||||
| Device | Notes |
|
||||
| --------- | --------------- |
|
||||
| AS6C62256 | Alliance Memory |
|
||||
| CY62256 | Cypress |
|
||||
| HM62256 | Hitachi |
|
||||
| KM62256 | Samsung |
|
||||
| IS62C256 | ISSI |
|
||||
|
||||
---
|
||||
|
||||
## 13. Common Use Cases
|
||||
|
||||
* Main RAM for 6502 / Z80 systems
|
||||
* Video buffers and frame memory
|
||||
* Embedded systems requiring fast R/W memory
|
||||
* Retrocomputer SBC designs
|
||||
|
||||
---
|
||||
|
||||
## 14. References
|
||||
|
||||
* <https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf>
|
||||
* <https://www.futurlec.com/Datasheet/Memory/62256.pdf>
|
||||
* <https://www.malinov.com/sergeys-blog/homebrew-notes.html>
|
||||
|
||||
---
|
||||
177
skills/legacy-circuit-mockups/references/7400-series.md
Normal file
177
skills/legacy-circuit-mockups/references/7400-series.md
Normal file
@@ -0,0 +1,177 @@
|
||||
# 7400-Series Logic ICs Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **7400-series** is a large family of **digital logic integrated circuits** originally implemented in **TTL (Transistor-Transistor Logic)** and later expanded to include **CMOS-compatible variants**. These devices provide fundamental building blocks such as gates, flip-flops, counters, multiplexers, decoders, and bus transceivers.
|
||||
|
||||
7400-series ICs are widely used in **retrocomputing**, **6502/Z80 systems**, **glue logic**, and educational designs.
|
||||
|
||||
---
|
||||
|
||||
## 2. Logic Families
|
||||
|
||||
| Family | Technology | Notes |
|
||||
| ------- | ----------------------- | ----------------------- |
|
||||
| 74xx | TTL | Original bipolar TTL |
|
||||
| 74LSxx | Low-power Schottky TTL | Faster, lower power |
|
||||
| 74HCTxx | CMOS (TTL-level inputs) | Ideal for mixed systems |
|
||||
| 74HCxx | CMOS | Wide voltage range |
|
||||
| 74ACTxx | Advanced CMOS TTL-level | Very fast |
|
||||
|
||||
---
|
||||
|
||||
## 3. Electrical Characteristics (Typical)
|
||||
|
||||
| Parameter | TTL | CMOS |
|
||||
| ----------------- | ------- | ------------------- |
|
||||
| VCC | 5 V | 2-6 V (5 V typical) |
|
||||
| Input HIGH | ≥ 2.0 V | ≥ 0.7xVCC |
|
||||
| Input LOW | ≤ 0.8 V | ≤ 0.3xVCC |
|
||||
| Fan-out | ~10 | Very high |
|
||||
| Power consumption | Higher | Lower |
|
||||
|
||||
---
|
||||
|
||||
## 4. Standard Package Types
|
||||
|
||||
| Package | Pins | Notes |
|
||||
| ------- | ---------- | ------------------- |
|
||||
| DIP | 14, 16, 20 | Breadboard-friendly |
|
||||
| SOIC | 14, 16, 20 | Surface-mount |
|
||||
| TSSOP | 14, 16 | Compact SMT |
|
||||
|
||||
---
|
||||
|
||||
## 5. Common Logic Categories
|
||||
|
||||
### 5.1 Basic Logic Gates
|
||||
|
||||
| IC | Function |
|
||||
| ---- | ----------------- |
|
||||
| 7400 | Quad 2-input NAND |
|
||||
| 7402 | Quad 2-input NOR |
|
||||
| 7404 | Hex inverter |
|
||||
| 7408 | Quad 2-input AND |
|
||||
| 7432 | Quad 2-input OR |
|
||||
| 7486 | Quad 2-input XOR |
|
||||
|
||||
---
|
||||
|
||||
### 5.2 Latches and Flip-Flops
|
||||
|
||||
| IC | Function |
|
||||
| ----- | --------------------- |
|
||||
| 7474 | Dual D-type flip-flop |
|
||||
| 7473 | Dual JK flip-flop |
|
||||
| 7475 | Quad latch |
|
||||
| 74175 | Quad D-type FF |
|
||||
|
||||
---
|
||||
|
||||
### 5.3 Counters and Registers
|
||||
|
||||
| IC | Function |
|
||||
| ----- | ------------------------------------- |
|
||||
| 74161 | Synchronous 4-bit counter |
|
||||
| 74163 | Synchronous binary counter |
|
||||
| 74193 | Up/down counter |
|
||||
| 74164 | Serial-in/parallel-out shift register |
|
||||
| 74165 | Parallel-in/serial-out shift register |
|
||||
|
||||
---
|
||||
|
||||
### 5.4 Decoders and Multiplexers
|
||||
|
||||
| IC | Function |
|
||||
| ----- | ----------------------- |
|
||||
| 74138 | 3-to-8 decoder |
|
||||
| 74139 | Dual 2-to-4 decoder |
|
||||
| 74151 | 8-to-1 multiplexer |
|
||||
| 74157 | Quad 2-to-1 multiplexer |
|
||||
|
||||
---
|
||||
|
||||
### 5.5 Bus Interface and Glue Logic
|
||||
|
||||
| IC | Function |
|
||||
| ----- | ----------------------------------- |
|
||||
| 74244 | Octal buffer / line driver |
|
||||
| 74245 | Octal bidirectional bus transceiver |
|
||||
| 74373 | Octal transparent latch |
|
||||
| 74574 | Octal D-type FF |
|
||||
|
||||
---
|
||||
|
||||
## 6. Pin Numbering Convention
|
||||
|
||||
* DIP packages use **counter-clockwise numbering**
|
||||
* Pin 1 identified by notch or dot
|
||||
|
||||
```text
|
||||
________
|
||||
1 °| |° 14
|
||||
2 °| |° 13
|
||||
3 °| |° 12
|
||||
4 °| |° 11
|
||||
5 °| |° 10
|
||||
6 °| |° 9
|
||||
7 °|________|° 8
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 7. Power and Ground Pins
|
||||
|
||||
| Package | VCC | GND |
|
||||
| ------- | --- | --- |
|
||||
| DIP-14 | 14 | 7 |
|
||||
| DIP-16 | 16 | 8 |
|
||||
| DIP-20 | 20 | 10 |
|
||||
|
||||
---
|
||||
|
||||
## 8. Timing Characteristics (General)
|
||||
|
||||
| Parameter | TTL | CMOS |
|
||||
| ----------------- | ------- | -------- |
|
||||
| Propagation delay | 5-15 ns | 8-25 ns |
|
||||
| Max frequency | ~25 MHz | ~50+ MHz |
|
||||
|
||||
---
|
||||
|
||||
## 9. Interfacing Notes
|
||||
|
||||
* TTL outputs reliably drive TTL inputs
|
||||
* CMOS inputs must not float
|
||||
* Use **74HCT** when interfacing CMOS with TTL signals
|
||||
* Decoupling capacitors (0.1 µF) required per IC
|
||||
|
||||
---
|
||||
|
||||
## 10. Typical Retrocomputer Applications
|
||||
|
||||
* Address decoding
|
||||
* Chip-select generation
|
||||
* Bus buffering
|
||||
* Clock gating and control
|
||||
* State machines
|
||||
|
||||
---
|
||||
|
||||
## 11. Absolute Maximum Ratings (Summary)
|
||||
|
||||
| Parameter | Rating |
|
||||
| ------------------- | --------------------- |
|
||||
| VCC | -0.5 V to +7.0 V |
|
||||
| Input voltage | -0.5 V to VCC + 0.5 V |
|
||||
| Storage temperature | -65 °C to +150 °C |
|
||||
|
||||
---
|
||||
|
||||
## 12. References
|
||||
|
||||
* <https://www.ti.com/lit/ds/symlink/sn74ls00.pdf>
|
||||
* <https://archive.org/details/TTLCookBook>
|
||||
* <https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide>
|
||||
|
||||
---
|
||||
258
skills/legacy-circuit-mockups/references/assembly-compiler.md
Normal file
258
skills/legacy-circuit-mockups/references/assembly-compiler.md
Normal file
@@ -0,0 +1,258 @@
|
||||
# 6502 SBC Assembly Compilation & ROM Build Specification
|
||||
|
||||
## Overview
|
||||
|
||||
This document defines a **complete specification for compiling 6502 assembly language** for a single-board computer consisting of:
|
||||
|
||||
* **MOS 6502 CPU**
|
||||
* **MOS 6522 VIA**
|
||||
* **AS6C62256 (32 KB SRAM)**
|
||||
* **AT28C256 (32 KB EEPROM / ROM)**
|
||||
* **DFRobot FIT0127 (HD44780-compatible 16x2 LCD)**
|
||||
|
||||
The focus is on **toolchain behavior, memory layout, ROM construction, and firmware conventions**, not electrical wiring.
|
||||
|
||||
---
|
||||
|
||||
## Target System Architecture
|
||||
|
||||
### Memory Map (Canonical)
|
||||
|
||||
```
|
||||
$0000-$00FF Zero Page (RAM)
|
||||
$0100-$01FF Stack (RAM)
|
||||
$0200-$7FFF General RAM (AS6C62256)
|
||||
$8000-$8FFF 6522 VIA I/O space
|
||||
$9000-$FFFF ROM (AT28C256)
|
||||
```
|
||||
|
||||
> Address decoding may mirror devices; assembler assumes this canonical layout.
|
||||
|
||||
---
|
||||
|
||||
## ROM Organization (AT28C256)
|
||||
|
||||
| Address | Purpose |
|
||||
| ----------- | -------------------- |
|
||||
| $9000-$FFEF | Program code + data |
|
||||
| $FFF0-$FFF9 | Optional system data |
|
||||
| $FFFA-$FFFB | NMI vector |
|
||||
| $FFFC-$FFFD | RESET vector |
|
||||
| $FFFE-$FFFF | IRQ/BRK vector |
|
||||
|
||||
ROM image size: **32,768 bytes**
|
||||
|
||||
---
|
||||
|
||||
## Reset & Startup Convention
|
||||
|
||||
On reset:
|
||||
|
||||
1. CPU fetches RESET vector at `$FFFC`
|
||||
2. Code initializes stack pointer
|
||||
3. Zero-page variables initialized
|
||||
4. VIA configured
|
||||
5. LCD initialized
|
||||
6. Main program entered
|
||||
|
||||
---
|
||||
|
||||
## Assembler Requirements
|
||||
|
||||
Assembler **MUST** support:
|
||||
|
||||
* `.org` absolute addressing
|
||||
* Symbolic labels
|
||||
* Binary output (`.bin`)
|
||||
* Little-endian word emission
|
||||
* Zero-page optimization
|
||||
|
||||
Recommended assemblers:
|
||||
|
||||
* **ca65** (cc65 toolchain)
|
||||
* **vasm6502**
|
||||
* **64tass**
|
||||
|
||||
---
|
||||
|
||||
## Assembly Source Structure
|
||||
|
||||
```asm
|
||||
;---------------------------
|
||||
; Reset Vector Entry Point
|
||||
;---------------------------
|
||||
.org $9000
|
||||
RESET:
|
||||
sei
|
||||
cld
|
||||
ldx #$FF
|
||||
txs
|
||||
jsr init_via
|
||||
jsr init_lcd
|
||||
MAIN:
|
||||
jsr lcd_print
|
||||
jmp MAIN
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Vector Table Definition
|
||||
|
||||
```asm
|
||||
.org $FFFA
|
||||
.word nmi_handler
|
||||
.word RESET
|
||||
.word irq_handler
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 6522 VIA Programming Model
|
||||
|
||||
### Register Map (Base = $8000)
|
||||
|
||||
| Offset | Register |
|
||||
| ------ | -------- |
|
||||
| $0 | ORB |
|
||||
| $1 | ORA |
|
||||
| $2 | DDRB |
|
||||
| $3 | DDRA |
|
||||
| $4 | T1CL |
|
||||
| $5 | T1CH |
|
||||
| $6 | T1LL |
|
||||
| $7 | T1LH |
|
||||
| $8 | T2CL |
|
||||
| $9 | T2CH |
|
||||
| $B | ACR |
|
||||
| $C | PCR |
|
||||
| $D | IFR |
|
||||
| $E | IER |
|
||||
|
||||
---
|
||||
|
||||
## LCD Interface Convention
|
||||
|
||||
### LCD Wiring Assumption
|
||||
|
||||
| LCD | VIA |
|
||||
| ----- | ------- |
|
||||
| D4-D7 | PB4-PB7 |
|
||||
| RS | PA0 |
|
||||
| E | PA1 |
|
||||
| R/W | GND |
|
||||
|
||||
4-bit mode assumed.
|
||||
|
||||
---
|
||||
|
||||
## LCD Initialization Sequence
|
||||
|
||||
```asm
|
||||
lcd_init:
|
||||
lda #$33
|
||||
jsr lcd_cmd
|
||||
lda #$32
|
||||
jsr lcd_cmd
|
||||
lda #$28
|
||||
jsr lcd_cmd
|
||||
lda #$0C
|
||||
jsr lcd_cmd
|
||||
lda #$06
|
||||
jsr lcd_cmd
|
||||
lda #$01
|
||||
jsr lcd_cmd
|
||||
rts
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## LCD Command/Data Interface
|
||||
|
||||
| Operation | RS | Data |
|
||||
| --------- | -- | --------------- |
|
||||
| Command | 0 | Instruction |
|
||||
| Data | 1 | ASCII character |
|
||||
|
||||
---
|
||||
|
||||
## Zero Page Usage Convention
|
||||
|
||||
| Address | Purpose |
|
||||
| ------- | ------------ |
|
||||
| $00-$0F | Scratch |
|
||||
| $10-$1F | LCD routines |
|
||||
| $20-$2F | VIA state |
|
||||
| $30-$FF | User-defined |
|
||||
|
||||
---
|
||||
|
||||
## RAM Usage (AS6C62256)
|
||||
|
||||
* Stack uses page `$01`
|
||||
* All RAM assumed volatile
|
||||
* No ROM shadowing
|
||||
|
||||
---
|
||||
|
||||
## Build Pipeline
|
||||
|
||||
### Step 1: Assemble
|
||||
|
||||
```bash
|
||||
ca65 main.asm -o main.o
|
||||
```
|
||||
|
||||
### Step 2: Link
|
||||
|
||||
```bash
|
||||
ld65 -C rom.cfg main.o -o rom.bin
|
||||
```
|
||||
|
||||
### Step 3: Pad ROM
|
||||
|
||||
Ensure `rom.bin` is exactly **32768 bytes**.
|
||||
|
||||
---
|
||||
|
||||
## EEPROM Programming
|
||||
|
||||
* Target device: **AT28C256**
|
||||
* Programmer: **MiniPro / T48**
|
||||
* Verify after write
|
||||
|
||||
---
|
||||
|
||||
## Emulator Expectations
|
||||
|
||||
Emulator must:
|
||||
|
||||
* Load ROM at `$9000-$FFFF`
|
||||
* Emulate VIA I/O side effects
|
||||
* Render LCD output
|
||||
* Honor RESET vector
|
||||
|
||||
---
|
||||
|
||||
## Testing Checklist
|
||||
|
||||
* Reset vector execution
|
||||
* VIA register writes
|
||||
* LCD displays correct text
|
||||
* Stack operations valid
|
||||
* ROM image maps correctly
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
* [MOS 6502 Programming Manual](http://archive.6502.org/datasheets/synertek_programming_manual.pdf)
|
||||
* [MOS 6522 VIA Datasheet](http://archive.6502.org/datasheets/mos_6522_preliminary_nov_1977.pdf)
|
||||
* [AT28C256 Datasheet](https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/AT28C256-Industrial-Grade-256-Kbit-Paged-Parallel-EEPROM-Data-Sheet-DS20006386.pdf)
|
||||
* [HD44780 LCD Datasheet](https://www.futurlec.com/LED/LCD16X2BLa.shtml)
|
||||
* [cc65 Toolchain Docs](https://cc65.github.io/doc/cc65.html)
|
||||
|
||||
---
|
||||
|
||||
## Notes
|
||||
|
||||
This specification is intentionally **end-to-end**: from assembly source to EEPROM image to running hardware or emulator. It defines a stable contract so ROMs, emulators, and real SBCs behave identically.
|
||||
226
skills/legacy-circuit-mockups/references/assembly-language.md
Normal file
226
skills/legacy-circuit-mockups/references/assembly-language.md
Normal file
@@ -0,0 +1,226 @@
|
||||
# 6502 Assembly Language with AT28C256 EEPROM
|
||||
|
||||
A practical specification for writing **6502/65C02 assembly language programs** intended to be stored in and executed from an **AT28C256 (32 KB) parallel EEPROM** in single-board computers (SBCs) and retro systems.
|
||||
|
||||
---
|
||||
|
||||
## 1. Scope and Assumptions
|
||||
|
||||
This document assumes:
|
||||
|
||||
* A **6502-family CPU** (6502, 65C02, or compatible)
|
||||
* Program code stored in an **AT28C256 (32K x 8) EEPROM**
|
||||
* Memory-mapped I/O (e.g., 6522 VIA)
|
||||
* Reset and interrupt vectors located in EEPROM
|
||||
* External RAM mapped elsewhere (e.g., 62256 SRAM)
|
||||
|
||||
---
|
||||
|
||||
## 2. AT28C256 EEPROM Overview
|
||||
|
||||
| Parameter | Value |
|
||||
| -------------- | ------------------- |
|
||||
| Capacity | 32 KB (32768 bytes) |
|
||||
| Address Lines | A0-A14 |
|
||||
| Data Lines | D0-D7 |
|
||||
| Access Time | ~150 ns |
|
||||
| Supply Voltage | 5 V |
|
||||
| Package | DIP-28 / PLCC |
|
||||
|
||||
### Typical Memory Map Usage
|
||||
|
||||
| Address Range | Usage |
|
||||
| ------------- | ----------------------- |
|
||||
| `$8000-$FFFF` | EEPROM (code + vectors) |
|
||||
| `$FFFA-$FFFF` | Interrupt vectors |
|
||||
|
||||
---
|
||||
|
||||
## 3. 6502 Memory Map Example
|
||||
|
||||
```
|
||||
$0000-$00FF Zero Page (RAM)
|
||||
$0100-$01FF Stack
|
||||
$0200-$7FFF RAM / I/O
|
||||
$8000-$FFFF AT28C256 EEPROM
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 4. Reset and Interrupt Vectors
|
||||
|
||||
The 6502 reads vectors from the **top of memory**:
|
||||
|
||||
| Vector | Address | Description |
|
||||
| ------- | ------------- | ---------------------- |
|
||||
| NMI | `$FFFA-$FFFB` | Non-maskable interrupt |
|
||||
| RESET | `$FFFC-$FFFD` | Reset entry point |
|
||||
| IRQ/BRK | `$FFFE-$FFFF` | Maskable interrupt |
|
||||
|
||||
### Vector Definition Example
|
||||
|
||||
```asm
|
||||
.org $FFFA
|
||||
.word nmi_handler
|
||||
.word reset
|
||||
.word irq_handler
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 5. Assembly Program Structure
|
||||
|
||||
### Typical Layout
|
||||
|
||||
```asm
|
||||
.org $8000
|
||||
|
||||
reset:
|
||||
sei ; Disable IRQs
|
||||
cld ; Clear decimal mode
|
||||
ldx #$FF
|
||||
txs ; Initialize stack
|
||||
|
||||
main:
|
||||
jmp main
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 6. Essential 6502 Instructions
|
||||
|
||||
### Registers
|
||||
|
||||
| Register | Purpose |
|
||||
| -------- | ---------------- |
|
||||
| A | Accumulator |
|
||||
| X, Y | Index registers |
|
||||
| SP | Stack pointer |
|
||||
| PC | Program counter |
|
||||
| P | Processor status |
|
||||
|
||||
### Common Instructions
|
||||
|
||||
| Instruction | Function |
|
||||
| ----------- | ---------------------- |
|
||||
| LDA/STA | Load/store accumulator |
|
||||
| LDX/LDY | Load index registers |
|
||||
| JMP/JSR | Jump / subroutine |
|
||||
| RTS | Return from subroutine |
|
||||
| BEQ/BNE | Conditional branch |
|
||||
| SEI/CLI | Disable/enable IRQ |
|
||||
|
||||
---
|
||||
|
||||
## 7. Addressing Modes (Common)
|
||||
|
||||
| Mode | Example | Notes |
|
||||
| --------- | ------------- | ------------ |
|
||||
| Immediate | `LDA #$01` | Constant |
|
||||
| Zero Page | `LDA $00` | Fast |
|
||||
| Absolute | `LDA $8000` | Full address |
|
||||
| Indexed | `LDA $2000,X` | Tables |
|
||||
| Indirect | `JMP ($FFFC)` | Vectors |
|
||||
|
||||
---
|
||||
|
||||
## 8. Writing Code for EEPROM Execution
|
||||
|
||||
### Key Considerations
|
||||
|
||||
* Code is **read-only at runtime**
|
||||
* Self-modifying code not recommended
|
||||
* Place jump tables and constants in EEPROM
|
||||
* Use RAM for variables and stack
|
||||
|
||||
### Zero Page Variable Example
|
||||
|
||||
```asm
|
||||
counter = $00
|
||||
|
||||
lda #$00
|
||||
sta counter
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 9. Timing and Performance
|
||||
|
||||
* EEPROM access time must meet CPU clock requirements
|
||||
* AT28C256 supports ~1 MHz comfortably
|
||||
* Faster clocks may require wait states or ROM shadowing
|
||||
|
||||
---
|
||||
|
||||
## 10. Example: Simple LED Toggle (Memory-Mapped I/O)
|
||||
|
||||
```asm
|
||||
PORTB = $6000
|
||||
DDRB = $6002
|
||||
|
||||
.org $8000
|
||||
reset:
|
||||
sei
|
||||
ldx #$FF
|
||||
txs
|
||||
|
||||
lda #$FF
|
||||
sta DDRB
|
||||
|
||||
loop:
|
||||
lda #$FF
|
||||
sta PORTB
|
||||
jsr delay
|
||||
lda #$00
|
||||
sta PORTB
|
||||
jsr delay
|
||||
jmp loop
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 11. Assembling and Programming Workflow
|
||||
|
||||
1. Write source (`.asm`)
|
||||
2. Assemble to binary
|
||||
3. Pad or relocate to `$8000`
|
||||
4. Program AT28C256 via T48 / minipro
|
||||
5. Insert EEPROM and reset CPU
|
||||
|
||||
---
|
||||
|
||||
## 12. Assembler Directives (Common)
|
||||
|
||||
| Directive | Purpose |
|
||||
| ---------- | --------------------------- |
|
||||
| `.org` | Set program origin |
|
||||
| `.byte` | Define byte |
|
||||
| `.word` | Define word (little-endian) |
|
||||
| `.include` | Include file |
|
||||
| `.equ` | Constant definition |
|
||||
|
||||
---
|
||||
|
||||
## 13. Common Mistakes
|
||||
|
||||
| Issue | Result |
|
||||
| -------------------------- | ------------------ |
|
||||
| Missing vectors | CPU hangs on reset |
|
||||
| Wrong `.org` | Code not executed |
|
||||
| Using RAM addresses in ROM | Crash |
|
||||
| Stack not initialized | Undefined behavior |
|
||||
|
||||
---
|
||||
|
||||
## 14. Reference Links
|
||||
|
||||
* [https://www.masswerk.at/6502/6502_instruction_set.html](https://www.masswerk.at/6502/6502_instruction_set.html)
|
||||
* [https://www.nesdev.org/wiki/6502](https://www.nesdev.org/wiki/6502)
|
||||
* [https://www.westerndesigncenter.com/wdc/documentation](https://www.westerndesigncenter.com/wdc/documentation)
|
||||
* [https://en.wikipedia.org/wiki/MOS_Technology_6502](https://en.wikipedia.org/wiki/MOS_Technology_6502)
|
||||
|
||||
---
|
||||
|
||||
**Document Scope:** 6502 assembly stored in AT28C256 EEPROM
|
||||
**Audience:** Retrocomputing, SBC designers, embedded hobbyists
|
||||
**Status:** Stable reference
|
||||
@@ -0,0 +1,86 @@
|
||||
# Basic Electronic Components
|
||||
|
||||
This document covers four fundamental electronic components: Resistors, Capacitors, Buttons, and Switches, including common values, formulas, and types.
|
||||
|
||||
---
|
||||
|
||||
## 1. Resistors (R)
|
||||
|
||||
Resistors limit the flow of electrical current and dissipate energy as heat.
|
||||
|
||||
### Common Formulas
|
||||
|
||||
* **Ohm's Law:** $V = I \times R$ (Voltage = Current $\times$ Resistance)
|
||||
* **Series Resistance:** $R_{total} = R_1 + R_2 + ... + R_n$
|
||||
* **Parallel Resistance:** $\frac{1}{R_{total}} = \frac{1}{R_1} + \frac{1}{R_2} + ... + \frac{1}{R_n}$
|
||||
|
||||
### Common Values (E12/E24 Series - 5% Tolerance)
|
||||
|
||||
Values are multiplied by powers of 10 (e.g., 10$\Omega$, 100$\Omega$, 1k$\Omega$, 10k$\Omega$, 100k$\Omega$, 1M$\Omega$):
|
||||
**1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1**
|
||||
|
||||
---
|
||||
|
||||
## 2. Capacitors (C)
|
||||
|
||||
Capacitors store electrical charge in an electric field.
|
||||
|
||||
### Common Formulas
|
||||
|
||||
* **Capacitance:** $C = \frac{Q}{V}$ (Charge / Voltage)
|
||||
* **Current:** $i = C \frac{dV}{dt}$
|
||||
* **Parallel Capacitance:** $C_{total} = C_1 + C_2 + ... + C_n$
|
||||
* **Series Capacitance:** $\frac{1}{C_{total}} = \frac{1}{C_1} + \frac{1}{C_2} + ... + \frac{1}{C_n}$
|
||||
* **Energy Stored:** $W = \frac{1}{2} C V^2$
|
||||
|
||||
### Common Values
|
||||
|
||||
* **Ceramic (picoFarads/nanoFarads):** 10pF, 22pF, 100pF, 1nF, 10nF, 100nF (often labeled "104")
|
||||
* **Electrolytic (microFarads):** 1µF, 10µF, 22µF, 47µF, 100µF, 220µF, 470µF, 1000µF
|
||||
|
||||
---
|
||||
|
||||
## 3. Buttons (Push Button)
|
||||
|
||||
A momentary switch that completes a circuit only when pressed.
|
||||
|
||||
### Common Types
|
||||
|
||||
* **Normally Open (NO):** Circuit is open (off) until pushed.
|
||||
* **Normally Closed (NC):** Circuit is closed (on) until pushed.
|
||||
* **Tactile Switch:** Small, standard button for PCB mounting.
|
||||
|
||||
---
|
||||
|
||||
## 4. Switches (SW)
|
||||
|
||||
An electromechanical device that breaks or connects a circuit, staying in position until flipped.
|
||||
|
||||
### Common Types
|
||||
|
||||
* **SPST:** Single Pole, Single Throw (On/Off)
|
||||
* **SPDT:** Single Pole, Double Throw (Toggle between two paths)
|
||||
* **DPST/DPDT:** Double Pole variants (controls two independent circuits simultaneously)
|
||||
* **DIP Switch:** Small array of switches for circuit boards.
|
||||
|
||||
---
|
||||
|
||||
## Quick Reference Summary Table
|
||||
|
||||
| Component | Symbol (Ref) | Key Formula | Common Use |
|
||||
| :--- | :--- | :--- | :--- |
|
||||
| **Resistor** | Zigzag / Box | $V=IR$ | Current limiting, voltage divider |
|
||||
| **Capacitor**| Two Parallel Lines| $i=C \frac{dV}{dt}$ | Filtering, timing, coupling |
|
||||
| **Button** | Momentary | N/A | User input (momentary) |
|
||||
| **Switch** | Toggle/Lever | N/A | Power control, signal routing |
|
||||
|
||||
---
|
||||
|
||||
## Common Suffixes
|
||||
|
||||
* **k** = kilo ($10^3$)
|
||||
* **M** = Mega ($10^6$)
|
||||
* **m** = milli ($10^{-3}$)
|
||||
* **µ** = micro ($10^{-6}$)
|
||||
* **n** = nano ($10^{-9}$)
|
||||
* **p** = pico ($10^{-12}$)
|
||||
214
skills/legacy-circuit-mockups/references/breadboard.md
Normal file
214
skills/legacy-circuit-mockups/references/breadboard.md
Normal file
@@ -0,0 +1,214 @@
|
||||
# Solderless Breadboard
|
||||
|
||||
A practical Markdown specification and reference for **common solderless breadboards**, intended for electronics prototyping, education, and hobbyist development.
|
||||
|
||||
---
|
||||
|
||||
## 1. Overview
|
||||
|
||||
A **solderless breadboard** is a reusable prototyping platform that allows electronic components to be interconnected without soldering. Connections are made via internal spring clips.
|
||||
|
||||
### Typical Uses
|
||||
|
||||
* Rapid circuit prototyping
|
||||
* Educational labs
|
||||
* Logic and microcontroller experiments
|
||||
* Low-power analog and digital circuits
|
||||
|
||||
### Not Suitable For
|
||||
|
||||
* High current (>1A)
|
||||
* High voltage (>36V)
|
||||
* RF / high-frequency designs
|
||||
* Vibration-prone or permanent installations
|
||||
|
||||
---
|
||||
|
||||
## 2. Physical Construction
|
||||
|
||||
### Materials
|
||||
|
||||
* ABS or polystyrene body
|
||||
* Phosphor bronze or nickel-plated spring contacts
|
||||
* Adhesive backing (optional)
|
||||
|
||||
### Standard Hole Pitch
|
||||
|
||||
* **2.54 mm (0.1 in)** - compatible with DIP ICs and standard headers
|
||||
|
||||
### Contact Characteristics
|
||||
|
||||
| Parameter | Typical Value |
|
||||
| ------------------ | ------------- |
|
||||
| Contact resistance | 10-50 mΩ |
|
||||
| Insertion cycles | ~5,000 |
|
||||
| Wire gauge | 20-28 AWG |
|
||||
|
||||
---
|
||||
|
||||
## 3. Internal Electrical Connections
|
||||
|
||||
### Terminal Strips (Main Area)
|
||||
|
||||
* Rows of **5 interconnected holes**
|
||||
* Horizontal connectivity
|
||||
* Center trench isolates left and right halves
|
||||
|
||||
```
|
||||
A B C D E | F G H I J
|
||||
──────────┼──────────
|
||||
Connected | Connected
|
||||
```
|
||||
|
||||
### Power Rails
|
||||
|
||||
* Vertical buses on each side
|
||||
* Often **split in the middle** (not always continuous)
|
||||
* Usually marked **red (+)** and **blue (-)**
|
||||
|
||||
```
|
||||
+ + + + + (may be split)
|
||||
- - - - -
|
||||
```
|
||||
|
||||
> ? Always verify continuity with a multimeter
|
||||
|
||||
---
|
||||
|
||||
## 4. Common Breadboard Sizes
|
||||
|
||||
| Type | Tie Points | Typical Use |
|
||||
| --------- | ---------- | ------------------------ |
|
||||
| Mini | 170 | Small test circuits |
|
||||
| Half-size | 400 | Microcontroller projects |
|
||||
| Full-size | 830 | Complex prototypes |
|
||||
| Modular | Variable | Expandable systems |
|
||||
|
||||
---
|
||||
|
||||
## 5. Component Compatibility
|
||||
|
||||
### Compatible Components
|
||||
|
||||
* DIP ICs (300 mil, 600 mil)
|
||||
* Axial resistors and diodes
|
||||
* LEDs
|
||||
* Tactile switches
|
||||
* Jumper wires
|
||||
* Pin headers
|
||||
|
||||
### Problematic Components
|
||||
|
||||
| Component | Issue |
|
||||
| -------------------- | -------------------------- |
|
||||
| TO-220 | Too wide / stress contacts |
|
||||
| SMD | Requires adapter |
|
||||
| Large electrolytics | Mechanical strain |
|
||||
| High-power resistors | Heat |
|
||||
|
||||
---
|
||||
|
||||
## 6. Electrical Characteristics
|
||||
|
||||
### Typical Limits
|
||||
|
||||
| Parameter | Recommended Max |
|
||||
| ------------------- | ------------------ |
|
||||
| Voltage | 30-36 V |
|
||||
| Current per contact | 500-1000 mA |
|
||||
| Frequency | <1 MHz (practical) |
|
||||
|
||||
### Parasitics (Approximate)
|
||||
|
||||
| Type | Value |
|
||||
| ----------- | ------------------- |
|
||||
| Capacitance | 1-5 pF per node |
|
||||
| Inductance | 10-20 nH per jumper |
|
||||
|
||||
---
|
||||
|
||||
## 7. Best Practices
|
||||
|
||||
### Power Distribution
|
||||
|
||||
* Run **ground and Vcc** to both sides
|
||||
* Bridge split power rails if needed
|
||||
* Decouple ICs with **0.1µF ceramic capacitors**
|
||||
|
||||
### Wiring
|
||||
|
||||
* Keep wires short and tidy
|
||||
* Use color coding:
|
||||
|
||||
* Red: Vcc
|
||||
* Black/Blue: GND
|
||||
* Yellow/White: Signals
|
||||
|
||||
### IC Placement
|
||||
|
||||
* Place DIP ICs **straddling the center trench**
|
||||
* Avoid forcing pins
|
||||
|
||||
---
|
||||
|
||||
## 8. Common Mistakes
|
||||
|
||||
| Mistake | Result |
|
||||
| ----------------------------- | ------------------ |
|
||||
| Assuming rails are continuous | Power loss |
|
||||
| Long jumper wires | Noise, instability |
|
||||
| No decoupling capacitors | Erratic behavior |
|
||||
| Exceeding current limits | Melted contacts |
|
||||
|
||||
---
|
||||
|
||||
## 9. Testing & Debugging
|
||||
|
||||
### Continuity Check
|
||||
|
||||
* Verify rails and rows using a multimeter
|
||||
|
||||
### Signal Integrity Tips
|
||||
|
||||
* Avoid breadboards for:
|
||||
|
||||
* High-speed clocks
|
||||
* ADC precision circuits
|
||||
|
||||
---
|
||||
|
||||
## 10. Typical Breadboard Layout Example
|
||||
|
||||
```
|
||||
[ + ] [ - ] Power Rails
|
||||
[ + ] [ - ]
|
||||
|
||||
A B C D E | F G H I J
|
||||
A B C D E | F G H I J
|
||||
A B C D E | F G H I J
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 11. Accessories
|
||||
|
||||
| Item | Purpose |
|
||||
| ----------------------- | ----------------- |
|
||||
| Jumper wire kits | Connections |
|
||||
| Breadboard power module | 5V / 3.3V supply |
|
||||
| Adhesive base | Mounting |
|
||||
| Logic probe | Digital debugging |
|
||||
|
||||
---
|
||||
|
||||
## 12. Reference Links
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Breadboard](https://en.wikipedia.org/wiki/Breadboard)
|
||||
* [https://learn.sparkfun.com/tutorials/how-to-use-a-breadboard](https://learn.sparkfun.com/tutorials/how-to-use-a-breadboard)
|
||||
* [https://www.allaboutcircuits.com/technical-articles/using-a-breadboard/](https://www.allaboutcircuits.com/technical-articles/using-a-breadboard/)
|
||||
|
||||
---
|
||||
|
||||
**Document Scope:** Solderless breadboard reference
|
||||
**Audience:** Hobbyist, student, engineer
|
||||
**Status:** Stable reference
|
||||
@@ -0,0 +1,281 @@
|
||||
# Common Breadboard Electronic Components
|
||||
|
||||
A practical reference for **breadboard-based electronics**, covering common components, formulas, tables, pinouts, and learning references. Suitable for beginners through intermediate hardware builders.
|
||||
|
||||
---
|
||||
|
||||
## 1. Resistors
|
||||
|
||||
### Description
|
||||
|
||||
Resistors limit current, divide voltage, and set bias points.
|
||||
|
||||
### Common Types
|
||||
|
||||
| Type | Notes | Typical Use |
|
||||
| ------------- | ----------- | ------------------ |
|
||||
| Carbon Film | Cheap, ±5% | General purpose |
|
||||
| Metal Film | Stable, ±1% | Precision circuits |
|
||||
| Wirewound | High power | Power dissipation |
|
||||
| Potentiometer | Adjustable | Volume, tuning |
|
||||
|
||||
### Standard Values (E12 Series)
|
||||
|
||||
`10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82 x 10^n`
|
||||
|
||||
### Color Code
|
||||
|
||||
| Band | Meaning |
|
||||
| ---- | ------------ |
|
||||
| 1 | First digit |
|
||||
| 2 | Second digit |
|
||||
| 3 | Multiplier |
|
||||
| 4 | Tolerance |
|
||||
|
||||
### Power Ratings
|
||||
|
||||
| Rating | Typical Size |
|
||||
| ------ | ------------------- |
|
||||
| 1/8 W | Small |
|
||||
| 1/4 W | Breadboard standard |
|
||||
| 1/2 W | Large |
|
||||
|
||||
### Formulas
|
||||
|
||||
* **Ohm's Law:** `V = I x R`
|
||||
* **Power:** `P = V × I = I² × R = V² / R`
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Resistor](https://en.wikipedia.org/wiki/Resistor)
|
||||
|
||||
---
|
||||
|
||||
## 2. Capacitors
|
||||
|
||||
### Description
|
||||
|
||||
Capacitors store electrical energy and block DC while passing AC.
|
||||
|
||||
### Common Types
|
||||
|
||||
| Type | Polarized | Typical Use |
|
||||
| ------------ | --------- | ------------------ |
|
||||
| Ceramic | No | Decoupling, bypass |
|
||||
| Electrolytic | Yes | Bulk filtering |
|
||||
| Tantalum | Yes | Compact filtering |
|
||||
| Film | No | Signal coupling |
|
||||
|
||||
### Common Values
|
||||
|
||||
| Range | Example |
|
||||
| ----- | ---------------- |
|
||||
| pF | 10pF, 100pF |
|
||||
| nF | 100nF (0.1µF) |
|
||||
| µF | 1µF, 10µF, 100µF |
|
||||
|
||||
### Voltage Rating Rule
|
||||
|
||||
> Capacitor voltage rating ≥ **2x circuit voltage**
|
||||
|
||||
### Formulas
|
||||
|
||||
* **Capacitive Reactance:** `Xc = 1 / (2πfC)`
|
||||
* **Energy Stored:** `E = ½ C V²`
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Capacitor](https://en.wikipedia.org/wiki/Capacitor)
|
||||
|
||||
---
|
||||
|
||||
## 3. Inductors
|
||||
|
||||
### Description
|
||||
|
||||
Inductors store energy in a magnetic field and resist changes in current.
|
||||
|
||||
### Common Types
|
||||
|
||||
| Type | Use |
|
||||
| ------------ | ----------------- |
|
||||
| Air-core | RF circuits |
|
||||
| Ferrite-core | Power filtering |
|
||||
| Choke | Noise suppression |
|
||||
|
||||
### Formula
|
||||
|
||||
* **Inductive Reactance:** `XL = 2πfL`
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Inductor](https://en.wikipedia.org/wiki/Inductor)
|
||||
|
||||
---
|
||||
|
||||
## 4. Diodes
|
||||
|
||||
### Description
|
||||
|
||||
Diodes allow current flow in one direction only.
|
||||
|
||||
### Common Types
|
||||
|
||||
| Type | Typical Part | Use |
|
||||
| --------- | ------------ | --------------------- |
|
||||
| Rectifier | 1N4007 | Power |
|
||||
| Signal | 1N4148 | Logic, fast switching |
|
||||
| Zener | 1N4733A | Voltage regulation |
|
||||
| Schottky | 1N5819 | Low drop |
|
||||
|
||||
### Key Parameters
|
||||
|
||||
| Parameter | Typical |
|
||||
| --------------- | -------------------------- |
|
||||
| Forward Voltage | 0.7V (Si), 0.3V (Schottky) |
|
||||
| Reverse Voltage | Device-specific |
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Diode](https://en.wikipedia.org/wiki/Diode)
|
||||
|
||||
---
|
||||
|
||||
## 5. LEDs (Light Emitting Diodes)
|
||||
|
||||
### Description
|
||||
|
||||
LEDs emit light when forward biased.
|
||||
|
||||
### Typical Forward Voltage
|
||||
|
||||
| Color | Vf |
|
||||
| ----- | -------- |
|
||||
| Red | 1.8-2.2V |
|
||||
| Green | 2.0-3.0V |
|
||||
| Blue | 3.0-3.3V |
|
||||
|
||||
### Current Limiting Resistor
|
||||
|
||||
`R = (V_supply - V_LED) / I_LED`
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Light-emitting_diode](https://en.wikipedia.org/wiki/Light-emitting_diode)
|
||||
|
||||
---
|
||||
|
||||
## 6. Transistors
|
||||
|
||||
### BJT (Bipolar Junction Transistor)
|
||||
|
||||
| Type | Example | Use |
|
||||
| ---- | ------- | ------------------------ |
|
||||
| NPN | 2N3904 | Switching, amplification |
|
||||
| PNP | 2N3906 | High-side switching |
|
||||
|
||||
**Key Formula:**
|
||||
|
||||
* `Ic ≈ β × Ib`
|
||||
|
||||
### MOSFET
|
||||
|
||||
| Type | Example | Use |
|
||||
| --------- | ------- | --------------------- |
|
||||
| N-channel | IRLZ44N | Logic-level switching |
|
||||
| P-channel | IRF9540 | High-side control |
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Transistor](https://en.wikipedia.org/wiki/Transistor)
|
||||
|
||||
---
|
||||
|
||||
## 7. Integrated Circuits (DIP)
|
||||
|
||||
### Common Logic Families
|
||||
|
||||
| Family | Voltage | Notes |
|
||||
| ----------- | ------- | ------------------- |
|
||||
| TTL (74LS) | 5V | Legacy |
|
||||
| CMOS (74HC) | 2-6V | Breadboard-friendly |
|
||||
|
||||
### Decoupling Rule
|
||||
|
||||
> Place **0.1µF ceramic capacitor** across Vcc and GND per IC
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Integrated_circuit](https://en.wikipedia.org/wiki/Integrated_circuit)
|
||||
|
||||
---
|
||||
|
||||
## 8. Switches & Buttons
|
||||
|
||||
| Type | Use |
|
||||
| ------- | --------------- |
|
||||
| Tactile | Momentary input |
|
||||
| Slide | Mode select |
|
||||
| Toggle | Power |
|
||||
|
||||
### Debounce (RC Approximation)
|
||||
|
||||
* Typical: `10kΩ + 100nF`
|
||||
|
||||
---
|
||||
|
||||
## 9. Breadboards
|
||||
|
||||
### Description
|
||||
|
||||
Solderless prototyping boards with internal bus connections.
|
||||
|
||||
### Internal Wiring
|
||||
|
||||
* Rows: connected horizontally (5 holes)
|
||||
* Rails: connected vertically (power)
|
||||
|
||||
### Limitations
|
||||
|
||||
* Not suitable for high-frequency or high-current circuits
|
||||
|
||||
### Reference
|
||||
|
||||
* [https://en.wikipedia.org/wiki/Breadboard](https://en.wikipedia.org/wiki/Breadboard)
|
||||
|
||||
---
|
||||
|
||||
## 10. Common Accessories
|
||||
|
||||
| Item | Purpose |
|
||||
| ---------------- | ----------------- |
|
||||
| Jumper wires | Connections |
|
||||
| USB power module | 5V / 3.3V supply |
|
||||
| Multimeter | Measurement |
|
||||
| Logic probe | Digital debugging |
|
||||
|
||||
---
|
||||
|
||||
## 11. Quick Reference Formulas
|
||||
|
||||
| Formula | Description |
|
||||
| --------------- | -------------------- |
|
||||
| `V = IR` | Ohm's Law |
|
||||
| `P = VI` | Power |
|
||||
| `Xc = 1/(2πfC)` | Capacitive reactance |
|
||||
| `XL = 2πfL` | Inductive reactance |
|
||||
| `E = ½CV²` | Capacitor energy |
|
||||
|
||||
---
|
||||
|
||||
## 12. Learning Resources
|
||||
|
||||
* [https://learn.sparkfun.com](https://learn.sparkfun.com)
|
||||
* [https://www.allaboutcircuits.com](https://www.allaboutcircuits.com)
|
||||
* [https://www.electronics-tutorials.ws](https://www.electronics-tutorials.ws)
|
||||
* [https://en.wikipedia.org/wiki/Electronics](https://en.wikipedia.org/wiki/Electronics)
|
||||
|
||||
---
|
||||
|
||||
**Document Purpose:** Practical breadboard electronics reference
|
||||
**Scope:** Hobbyist, education, prototyping
|
||||
@@ -0,0 +1,310 @@
|
||||
# Connecting Electronic Components
|
||||
|
||||
This guide provides step-by-step instructions for building electronic circuits on a breadboard. Each build progressively introduces new components and concepts.
|
||||
|
||||
---
|
||||
|
||||
## Basic Component Build Instructions
|
||||
|
||||
### Build 1 — Single LED
|
||||
|
||||
**Components:** Red LED, black jumper wire, red jumper wire, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A5** to **A14**.
|
||||
2. Insert the red jumper wire into the breadboard from **J5** to **J14**.
|
||||
3. Place the red LED into row 14 with the positive leg (the longer of the two legs) on the right side, aligned with the red wire, and the negative leg on the left, aligned with the black wire.
|
||||
4. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you insert the battery, the LED will light up.
|
||||
|
||||
**Troubleshooting:**
|
||||
|
||||
- Is your LED inserted backwards?
|
||||
- Are the jumper wires in the same row as the LED leads?
|
||||
- Are the jumper wires in the same row as the battery terminals?
|
||||
|
||||
---
|
||||
|
||||
### Build 2 — Single Push Button
|
||||
|
||||
**Components:** Red LED, push button, black jumper wire, red jumper wire, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A5** to **A16**.
|
||||
2. Insert the red jumper wire into the breadboard from **J5** to **J12**.
|
||||
3. Place the red LED into the breadboard with the positive leg (the longer of the two legs) inserted into **H15** and the negative leg into **G17**.
|
||||
4. Place the push button horizontally in the middle of the breadboard so the bottom-left pin is on row 16 (aligned with the black jumper wire) and the top-right pin is on row 14 (aligned with the negative leg of the red LED).
|
||||
5. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you press the push button, the LED will light up.
|
||||
|
||||
**Troubleshooting:**
|
||||
|
||||
- Is your LED inserted backwards?
|
||||
- Are the jumper wires in the same row as the LED leads?
|
||||
- Are the jumper wires in the same row as the battery terminals?
|
||||
|
||||
---
|
||||
|
||||
### Build 3 — Photoresistor-Dimmed LED
|
||||
|
||||
**Components:** Green LED, photoresistor, black jumper wire, red jumper wire, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A5** to **A12**.
|
||||
2. Insert the red jumper wire into the breadboard from **J5** to **J13**.
|
||||
3. Place the green LED into the breadboard with the positive leg (the longer of the two legs) inserted into **F13** and the negative leg into **E13**.
|
||||
4. Insert the photoresistor into the breadboard from **C12** to **D13**.
|
||||
5. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you insert the battery, the LED will light up. Covering the photoresistor will cause the LED to dim.
|
||||
|
||||
---
|
||||
|
||||
### Build 4 — Double LED Push Button
|
||||
|
||||
**Components:** Red LED, green LED, 220Ω resistor, push button, black jumper wire, red jumper wire, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A5** to **A11**.
|
||||
2. Insert the red jumper wire into the breadboard from **J5** to **J11**.
|
||||
3. Insert the 220Ω resistor into the breadboard from **I11** to **I15**.
|
||||
4. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard.
|
||||
5. Place the red LED into the breadboard with the positive leg (the longer of the two legs) inserted into **C17** and the negative leg into **B11**.
|
||||
6. Place the green LED into the breadboard with the positive leg inserted into **G15** and the negative leg into **E11**.
|
||||
7. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you insert the battery, the green LED will light up. When you press the push button, the green LED will turn off and the red LED will light up.
|
||||
|
||||
### Build 5 - Photoresistor Blinking LEDs
|
||||
|
||||
- Insert the black jumper wire into the breadboard from A3 to A12.
|
||||
- Insert the red jumper wire into the breadboard from J3 to J12.
|
||||
- Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 12.
|
||||
- Insert a jumper wire into the breadboard connecting D15 to G12.
|
||||
- Insert a jumper wire into the breadboard connecting D13 to G14.
|
||||
- Insert the 1000Ω resistor into the breadboard from C14 to H17.
|
||||
- Insert the photoresistor into the breadboard from B14 to B15.
|
||||
- Insert the capacitor into the breadboard from A13 to B12.
|
||||
- Place the green LED into the breadboard with the positive leg (longer of the two legs) inserted into F17 and the negative leg into C12.
|
||||
- Place the red LED into the breadboard with the positive leg inserted into I12 and the negative leg into J17.
|
||||
- Insert the battery into its battery holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
When you insert the battery, both LED’s will begin rapidly blinking. Covering the photoresistor from light will slow the LEDs blinking frequency.
|
||||
|
||||
---
|
||||
|
||||
## 555 Timer IC Reference
|
||||
|
||||
The 555 timer is a versatile integrated circuit used in timing, pulse generation, and oscillator applications. The following sections provide pinout information and internal circuit details.
|
||||
|
||||
### 555 Pinout Diagram
|
||||
|
||||
```
|
||||
┌─────────────────────────────────────┐
|
||||
│ ● │
|
||||
│ #1 #8 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #2 #7 │
|
||||
│ ┌──┐ 555 TIMER ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #3 #6 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
│ #4 #5 │
|
||||
│ ┌──┐ ┌──┐ │
|
||||
│ │ │ │ │ │
|
||||
│ └──┘ └──┘ │
|
||||
└─────────────────────────────────────┘
|
||||
```
|
||||
|
||||
### 555 Pin Descriptions
|
||||
|
||||
| Pin | Symbol | Function |
|
||||
|:---:|:---:|:---|
|
||||
| 1 | GND | Ground reference (0V) |
|
||||
| 2 | TRIG | Trigger input — starts timing cycle when voltage drops below ⅓ Vcc |
|
||||
| 3 | OUT | Output — provides high or low signal |
|
||||
| 4 | RESET | Reset input (active low) — forces output low when grounded |
|
||||
| 5 | CONT | Control voltage — provides access to internal voltage divider (⅔ Vcc) |
|
||||
| 6 | THRES | Threshold input — ends timing cycle when voltage exceeds ⅔ Vcc |
|
||||
| 7 | DISCH | Discharge — open collector output for discharging timing capacitor |
|
||||
| 8 | Vcc | Supply voltage (+4.5V to +16V) |
|
||||
|
||||
### 555 Internal Block Diagram
|
||||
|
||||
```mermaid
|
||||
flowchart TB
|
||||
subgraph IC["555 Timer IC"]
|
||||
direction TB
|
||||
|
||||
subgraph DIVIDER["Voltage Divider"]
|
||||
R1["R (5kΩ)"]
|
||||
R2["R (5kΩ)"]
|
||||
R3["R (5kΩ)"]
|
||||
R1 --- R2 --- R3
|
||||
end
|
||||
|
||||
COMP1["Comparator 1<br/>(Threshold)"]
|
||||
COMP2["Comparator 2<br/>(Trigger)"]
|
||||
FF["Flip-Flop<br/>S-R"]
|
||||
OUT_STAGE["Output<br/>Stage"]
|
||||
DISCH_TR["Discharge<br/>Transistor"]
|
||||
VREF["Vref"]
|
||||
end
|
||||
|
||||
PIN8["Pin 8<br/>Vcc"] --> R1
|
||||
R3 --> PIN1["Pin 1<br/>GND"]
|
||||
|
||||
R1 -.->|"2/3 Vcc"| COMP1
|
||||
R2 -.->|"1/3 Vcc"| COMP2
|
||||
|
||||
PIN6["Pin 6<br/>Threshold"] --> COMP1
|
||||
PIN2["Pin 2<br/>Trigger"] --> COMP2
|
||||
|
||||
COMP1 -->|R| FF
|
||||
COMP2 -->|S| FF
|
||||
|
||||
FF --> OUT_STAGE
|
||||
FF --> DISCH_TR
|
||||
|
||||
OUT_STAGE --> PIN3["Pin 3<br/>Output"]
|
||||
DISCH_TR --> PIN7["Pin 7<br/>Discharge"]
|
||||
|
||||
PIN4["Pin 4<br/>Reset"] --> FF
|
||||
PIN5["Pin 5<br/>Control Voltage"] -.-> R2
|
||||
|
||||
style PIN1 fill:#000,color:#fff
|
||||
style PIN2 fill:#f96,color:#000
|
||||
style PIN3 fill:#6f6,color:#000
|
||||
style PIN4 fill:#f66,color:#000
|
||||
style PIN5 fill:#ff6,color:#000
|
||||
style PIN6 fill:#6ff,color:#000
|
||||
style PIN7 fill:#f6f,color:#000
|
||||
style PIN8 fill:#f00,color:#fff
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
### Build 6 — Push Button Buzzer
|
||||
|
||||
**Components:** 555 timer IC, piezo speaker, 220Ω resistor, 1000Ω resistor, capacitor, push button, jumper wires, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A1** to **A11**.
|
||||
2. Insert the red jumper wire into the breadboard from **J1** to **J11**.
|
||||
3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11.
|
||||
4. Insert a jumper wire into the breadboard connecting **D12** to **G13**.
|
||||
5. Insert a jumper wire into the breadboard connecting **D14** to **G11**.
|
||||
6. Insert the capacitor into the breadboard from **A12** to **B11**.
|
||||
7. Insert the 220Ω resistor into the breadboard from **C12** to **C13**.
|
||||
8. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard.
|
||||
9. Insert the piezo speaker into the breadboard with the positive pin in **A9** and the negative pin in **A6**.
|
||||
10. Insert the 1000Ω resistor into the breadboard from **E6** to **A13**.
|
||||
11. Insert a jumper wire into the breadboard connecting **C9** to **D15**.
|
||||
12. Insert a jumper wire into the breadboard connecting **G17** to **I11**.
|
||||
13. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you press the push button, the buzzer will sound.
|
||||
|
||||
---
|
||||
|
||||
### Build 7 — Photoresistor Theremin
|
||||
|
||||
**Components:** 555 timer IC, piezo speaker, photoresistor, 1000Ω resistor, capacitor, push button, jumper wires, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A1** to **A11**.
|
||||
2. Insert the red jumper wire into the breadboard from **J1** to **J11**.
|
||||
3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11.
|
||||
4. Insert a jumper wire into the breadboard connecting **D12** to **G13**.
|
||||
5. Insert a jumper wire into the breadboard connecting **D14** to **G11**.
|
||||
6. Insert the capacitor into the breadboard from **A12** to **B11**.
|
||||
7. Insert the photoresistor into the breadboard from **C12** to **C13**.
|
||||
8. Place the push button horizontally in the middle of the breadboard so the top pins are on row 15 and on opposite sides of the breadboard.
|
||||
9. Insert the piezo speaker into the breadboard with the positive pin in **A9** and the negative pin in **A6**.
|
||||
10. Insert the 1000Ω resistor into the breadboard from **E6** to **A13**.
|
||||
11. Insert a jumper wire into the breadboard connecting **C9** to **D15**.
|
||||
12. Insert a jumper wire into the breadboard connecting **G17** to **I11**.
|
||||
13. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you press the push button, the buzzer will sound. Covering the photoresistor will change the pitch of the buzzer.
|
||||
|
||||
---
|
||||
|
||||
### Build 8 — Potentiometer-Dimmed LED
|
||||
|
||||
**Components:** Green LED, potentiometer, 220Ω resistor, black jumper wire, red jumper wire, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A1** to **A13**.
|
||||
2. Insert the red jumper wire into the breadboard from **J1** to **J9**.
|
||||
3. Place the potentiometer with the two-pin side on the left, top pin in **E13** and bottom pin in **E15**.
|
||||
4. Insert the 220Ω resistor into the breadboard from **H9** to **H14**.
|
||||
5. Place the green LED into the breadboard with the positive leg (the longer of the two legs) inserted into **C15** and the negative leg in **B13**.
|
||||
6. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** When you insert the battery, the LED will turn on. Rotating the potentiometer will increase or decrease the brightness of the LED.
|
||||
|
||||
---
|
||||
|
||||
### Build 9 — Push Button RGB LED
|
||||
|
||||
**Components:** RGB LED (common cathode), three push buttons, two 220Ω resistors, black jumper wire, red jumper wire, jumper wires, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A1** to **B7**.
|
||||
2. Insert the red jumper wire into the breadboard from **J1** to **J7**.
|
||||
3. Insert the RGB LED into the breadboard from **A4** to **A8**. The longest of the four legs is the ground and should be in **A7**.
|
||||
4. Place three push buttons horizontally in the middle of the breadboard with pins at:
|
||||
- Button 1: **E9–F9** and **E11–F11**
|
||||
- Button 2: **E12–F12** and **E14–F14**
|
||||
- Button 3: **E15–F15** and **E17–F17**
|
||||
5. Insert a jumper wire into the breadboard connecting **C5** to **D9**.
|
||||
6. Insert a jumper wire into the breadboard connecting **C6** to **C12**.
|
||||
7. Insert a jumper wire into the breadboard connecting **B8** to **B15**.
|
||||
8. Insert the first 220Ω resistor into the breadboard from **G7** to **G11**.
|
||||
9. Insert the second 220Ω resistor into the breadboard from **H7** to **H14**.
|
||||
10. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** Pressing each push button will activate a different color channel of the RGB LED.
|
||||
|
||||
---
|
||||
|
||||
### Build 10 — Potentiometer-Controlled Buzzer
|
||||
|
||||
**Components:** 555 timer IC, piezo speaker, potentiometer, 220Ω resistor, capacitor, push button, jumper wires, battery with holder
|
||||
|
||||
**Steps:**
|
||||
|
||||
1. Insert the black jumper wire into the breadboard from **A1** to **A11**.
|
||||
2. Insert the red jumper wire into the breadboard from **J1** to **J11**.
|
||||
3. Place the 555 integrated circuit chip into the middle of the breadboard with the top pins on row 11.
|
||||
4. Insert a jumper wire into the breadboard connecting **D12** to **G13**.
|
||||
5. Insert a jumper wire into the breadboard connecting **D14** to **G11**.
|
||||
6. Insert the capacitor into the breadboard from **A12** to **B11**.
|
||||
7. Insert the piezo speaker into the breadboard from **A6** to **A9** (place the positive end on the bottom).
|
||||
8. Place the push button horizontally in the middle of the breadboard so the top pins are in **E15** and **F15**.
|
||||
9. Insert the 220Ω resistor into the breadboard from **E6** to **A13**.
|
||||
10. Insert a jumper wire into the breadboard connecting **E9** to **D15**.
|
||||
11. Insert a jumper wire into the breadboard connecting **G17** to **I11**.
|
||||
12. Place the potentiometer with the two-pin side on the right, top pin in **F7** and bottom pin in **F9**.
|
||||
13. Insert a jumper wire into the breadboard connecting **D8** to **B13**.
|
||||
14. Insert a jumper wire into the breadboard connecting **H7** to **C12**.
|
||||
15. Insert a jumper wire into the breadboard connecting **H9** to **D11**.
|
||||
16. Insert the battery into its holder and place it in the breadboard, connecting negative to black and positive to red.
|
||||
|
||||
**Result:** Pressing the push button will cause the buzzer to sound. Rotating the potentiometer will alter the pitch of the buzzer.
|
||||
@@ -0,0 +1,245 @@
|
||||
# AT28C256 EEPROM Emulation Specification
|
||||
|
||||
## Overview
|
||||
|
||||
This document specifies how to **emulate the AT28C256 (32 KB Parallel EEPROM)** in a 6502-based system emulator. The goal is *behavioral accuracy* suitable for SBCs, monitors, and real ROM images, not just generic file-backed storage.
|
||||
|
||||
The AT28C256 is commonly used as **ROM** in 6502 systems, but it is *electrically writable* and has timing behaviors that differ from SRAM.
|
||||
|
||||
---
|
||||
|
||||
## Chip Summary
|
||||
|
||||
| Parameter | Value |
|
||||
| -------------- | ---------------------- |
|
||||
| Capacity | 32 KB (256 Kbit) |
|
||||
| Organization | 32,768 x 8 |
|
||||
| Address Lines | A0-A14 |
|
||||
| Data Lines | D0-D7 |
|
||||
| Supply Voltage | 5V |
|
||||
| Typical Use | ROM / Firmware storage |
|
||||
|
||||
---
|
||||
|
||||
## Pin Definitions
|
||||
|
||||
| Pin | Name | Function |
|
||||
| ------ | ------------- | ---------------------- |
|
||||
| A0-A14 | Address | Byte address |
|
||||
| D0-D7 | Data | Data bus |
|
||||
| /CE | Chip Enable | Activates chip |
|
||||
| /OE | Output Enable | Enables output drivers |
|
||||
| /WE | Write Enable | Triggers write cycle |
|
||||
| VCC | +5V | Power |
|
||||
| GND | Ground | Reference |
|
||||
|
||||
---
|
||||
|
||||
## Read Cycle Behavior
|
||||
|
||||
A read occurs when:
|
||||
|
||||
```
|
||||
/CE = 0
|
||||
/OE = 0
|
||||
/WE = 1
|
||||
```
|
||||
|
||||
### Read Rules
|
||||
|
||||
* Address must be stable before `/OE` is asserted
|
||||
* Data appears on D0-D7 after access time (ignored in most emulators)
|
||||
* Output is **high-impedance** when `/OE = 1` or `/CE = 1`
|
||||
|
||||
### Emulator Behavior
|
||||
|
||||
```text
|
||||
if CE == 0 and OE == 0 and WE == 1:
|
||||
data_bus = memory[address]
|
||||
else:
|
||||
data_bus = Z
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Write Cycle Behavior
|
||||
|
||||
A write occurs when:
|
||||
|
||||
```
|
||||
/CE = 0
|
||||
/WE = 0
|
||||
```
|
||||
|
||||
(`/OE` is typically HIGH during writes)
|
||||
|
||||
### Important EEPROM Characteristics
|
||||
|
||||
* Writes are **not instantaneous**
|
||||
* Each write triggers an **internal programming cycle**
|
||||
* During programming, reads may return undefined data
|
||||
|
||||
---
|
||||
|
||||
## Write Timing Model (Simplified)
|
||||
|
||||
### Real Hardware
|
||||
|
||||
| Parameter | Typical |
|
||||
| --------------- | -------- |
|
||||
| Byte Write Time | ~200 µs |
|
||||
| Page Size | 64 bytes |
|
||||
| Page Write Time | ~10 ms |
|
||||
|
||||
### Emulator Simplification Options
|
||||
|
||||
#### Option A - Instant Writes (Common)
|
||||
|
||||
* Write immediately updates memory
|
||||
* No busy state
|
||||
* Recommended for early emulators
|
||||
|
||||
#### Option B - Cycle-Based Busy State (Advanced)
|
||||
|
||||
* Track a "write in progress" timer
|
||||
* Reads during write return last value or `0xFF`
|
||||
* Writes ignored until cycle completes
|
||||
|
||||
---
|
||||
|
||||
## Page Write Emulation (Optional)
|
||||
|
||||
* Page size: **64 bytes**
|
||||
* Writes within same page before timeout commit together
|
||||
* Crossing page boundary wraps within page (hardware quirk)
|
||||
|
||||
Simplified rule:
|
||||
|
||||
```text
|
||||
page_base = address & 0xFFC0
|
||||
page_offset = address & 0x003F
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Write Protection Behavior
|
||||
|
||||
Some systems treat EEPROM as **ROM-only** after programming.
|
||||
|
||||
Emulator may support:
|
||||
|
||||
* Read-only mode (writes ignored)
|
||||
* Programmable mode (writes allowed)
|
||||
* Runtime toggle (simulates programming jumper)
|
||||
|
||||
---
|
||||
|
||||
## Power-Up State
|
||||
|
||||
* EEPROM retains contents
|
||||
* No undefined data on power-up
|
||||
|
||||
Emulator should:
|
||||
|
||||
* Load contents from image file
|
||||
* Preserve data across resets
|
||||
|
||||
---
|
||||
|
||||
## Bus Contention Rules
|
||||
|
||||
| Condition | Behavior |
|
||||
| ------------------- | ----------------- |
|
||||
| /CE = 1 | Data bus = Z |
|
||||
| /OE = 1 | Data bus = Z |
|
||||
| /WE = 0 and /OE = 0 | Undefined (avoid) |
|
||||
|
||||
Emulator may:
|
||||
|
||||
* Prioritize write
|
||||
* Or flag invalid state
|
||||
|
||||
---
|
||||
|
||||
## Memory Mapping in 6502 Systems
|
||||
|
||||
Common layout:
|
||||
|
||||
```
|
||||
$0000-$7FFF RAM
|
||||
$8000-$FFFF AT28C256 EEPROM
|
||||
```
|
||||
|
||||
### Reset Vector Usage
|
||||
|
||||
| Vector | Address |
|
||||
| ------ | ----------- |
|
||||
| RESET | $FFFC-$FFFD |
|
||||
| NMI | $FFFA-$FFFB |
|
||||
| IRQ | $FFFE-$FFFF |
|
||||
|
||||
---
|
||||
|
||||
## Emulator API Model
|
||||
|
||||
```c
|
||||
typedef struct {
|
||||
uint8_t memory[32768];
|
||||
bool write_enabled;
|
||||
bool busy;
|
||||
uint32_t busy_cycles;
|
||||
} AT28C256;
|
||||
```
|
||||
|
||||
### Read
|
||||
|
||||
```c
|
||||
uint8_t eeprom_read(addr);
|
||||
```
|
||||
|
||||
### Write
|
||||
|
||||
```c
|
||||
void eeprom_write(addr, value);
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Recommended Emulator Defaults
|
||||
|
||||
| Feature | Setting |
|
||||
| ------------- | ----------- |
|
||||
| Write Delay | Disabled |
|
||||
| Page Mode | Disabled |
|
||||
| Write Protect | Enabled |
|
||||
| Persistence | File-backed |
|
||||
|
||||
---
|
||||
|
||||
## Testing Checklist
|
||||
|
||||
* Reset vector fetch
|
||||
* ROM reads under normal execution
|
||||
* Writes ignored in read-only mode
|
||||
* Correct address masking (15 bits)
|
||||
* No bus drive when disabled
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
* [AT28C256 Datasheet (Microchip)](https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/AT28C256-Industrial-Grade-256-Kbit-Paged-Parallel-EEPROM-Data-Sheet-DS20006386.pdf)
|
||||
* [Ben Eater 6502 Computer Series](https://eater.net/6502)
|
||||
* <https://www.youtube.com/watch?v=oO8_2JJV0B4>
|
||||
* [6502.org Memory Mapping Notes](https://6502.co.uk/lesson/memory-map)
|
||||
|
||||
---
|
||||
|
||||
## Notes
|
||||
|
||||
This specification intentionally mirrors **real hardware quirks** while allowing emulator authors to choose between simplicity and accuracy. It is suitable for:
|
||||
|
||||
* Educational emulators
|
||||
* SBC simulation
|
||||
* ROM development workflows
|
||||
* Integration with 6502 + 6522 + SRAM emulation
|
||||
251
skills/legacy-circuit-mockups/references/emulator-6502.md
Normal file
251
skills/legacy-circuit-mockups/references/emulator-6502.md
Normal file
@@ -0,0 +1,251 @@
|
||||
# 6502 CPU Emulation Specification
|
||||
|
||||
A technical Markdown specification for **emulating the MOS Technology 6502 CPU family**, suitable for software emulators, educational tools, testing frameworks, and retrocomputing projects.
|
||||
|
||||
---
|
||||
|
||||
## 1. Scope
|
||||
|
||||
This specification describes the functional requirements for emulating:
|
||||
|
||||
* MOS 6502
|
||||
* WDC 65C02 (where noted)
|
||||
|
||||
Out of scope:
|
||||
|
||||
* Cycle-exact analog behavior
|
||||
* Physical bus contention
|
||||
* Undocumented silicon defects (unless explicitly implemented)
|
||||
|
||||
---
|
||||
|
||||
## 2. CPU Overview
|
||||
|
||||
### Core Characteristics
|
||||
|
||||
| Feature | Value |
|
||||
| ------------- | ------------- |
|
||||
| Data width | 8-bit |
|
||||
| Address width | 16-bit |
|
||||
| Address space | 64 KB |
|
||||
| Endianness | Little-endian |
|
||||
| Clock | Single-phase |
|
||||
|
||||
---
|
||||
|
||||
## 3. Registers
|
||||
|
||||
| Register | Size | Description |
|
||||
| -------- | ------ | -------------------------- |
|
||||
| A | 8-bit | Accumulator |
|
||||
| X | 8-bit | Index register |
|
||||
| Y | 8-bit | Index register |
|
||||
| SP | 8-bit | Stack pointer (page $01xx) |
|
||||
| PC | 16-bit | Program counter |
|
||||
| P | 8-bit | Processor status flags |
|
||||
|
||||
### Status Flags (P)
|
||||
|
||||
| Bit | Name | Meaning |
|
||||
| --- | ---- | ----------------------------- |
|
||||
| 7 | N | Negative |
|
||||
| 6 | V | Overflow |
|
||||
| 5 | - | Unused (always 1 when pushed) |
|
||||
| 4 | B | Break |
|
||||
| 3 | D | Decimal |
|
||||
| 2 | I | IRQ disable |
|
||||
| 1 | Z | Zero |
|
||||
| 0 | C | Carry |
|
||||
|
||||
---
|
||||
|
||||
## 4. Memory Model
|
||||
|
||||
### Addressing
|
||||
|
||||
* 16-bit address bus (`$0000-$FFFF`)
|
||||
* Byte-addressable
|
||||
|
||||
### Required Emulator Interfaces
|
||||
|
||||
```text
|
||||
read(address) -> byte
|
||||
write(address, byte)
|
||||
```
|
||||
|
||||
### Stack Behavior
|
||||
|
||||
* Stack base: `$0100`
|
||||
* Push: `write($0100 + SP, value); SP--`
|
||||
* Pull: `SP++; value = read($0100 + SP)`
|
||||
|
||||
---
|
||||
|
||||
## 5. Reset and Interrupt Handling
|
||||
|
||||
### Reset Sequence
|
||||
|
||||
1. Set `I = 1`
|
||||
2. Set `SP = $FD`
|
||||
3. Clear `D`
|
||||
4. Load `PC` from `$FFFC-$FFFD`
|
||||
|
||||
### Interrupt Vectors
|
||||
|
||||
| Interrupt | Vector Address |
|
||||
| --------- | -------------- |
|
||||
| NMI | `$FFFA-$FFFB` |
|
||||
| RESET | `$FFFC-$FFFD` |
|
||||
| IRQ/BRK | `$FFFE-$FFFF` |
|
||||
|
||||
---
|
||||
|
||||
## 6. Instruction Fetch-Decode-Execute Cycle
|
||||
|
||||
### Execution Loop (Conceptual)
|
||||
|
||||
```text
|
||||
opcode = read(PC++)
|
||||
decode opcode
|
||||
fetch operands
|
||||
execute instruction
|
||||
update flags
|
||||
increment cycles
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 7. Addressing Modes
|
||||
|
||||
| Mode | Example | Notes |
|
||||
| ---------------- | ------------- | --------------------- |
|
||||
| Immediate | `LDA #$10` | Constant |
|
||||
| Zero Page | `LDA $20` | Wraps at $00FF |
|
||||
| Absolute | `LDA $2000` | Full address |
|
||||
| Indexed | `LDA $2000,X` | Optional page penalty |
|
||||
| Indirect | `JMP ($FFFC)` | Page wrap bug |
|
||||
| Indexed Indirect | `LDA ($20,X)` | ZP indexed |
|
||||
| Indirect Indexed | `LDA ($20),Y` | ZP pointer |
|
||||
|
||||
---
|
||||
|
||||
## 8. Instruction Set Requirements
|
||||
|
||||
### Categories
|
||||
|
||||
* Load/Store
|
||||
* Arithmetic (ADC, SBC)
|
||||
* Logic (AND, ORA, EOR)
|
||||
* Shifts & Rotates
|
||||
* Branches
|
||||
* Stack operations
|
||||
* System control
|
||||
|
||||
### Decimal Mode (NMOS 6502)
|
||||
|
||||
* Applies to `ADC` and `SBC`
|
||||
* Uses BCD arithmetic when `D = 1`
|
||||
|
||||
---
|
||||
|
||||
## 9. Flags Behavior Rules
|
||||
|
||||
| Instruction Type | Flags Affected |
|
||||
| ---------------- | -------------- |
|
||||
| Loads | N, Z |
|
||||
| ADC/SBC | N, V, Z, C |
|
||||
| CMP/CPX/CPY | N, Z, C |
|
||||
| INC/DEC | N, Z |
|
||||
| Shifts | N, Z, C |
|
||||
|
||||
---
|
||||
|
||||
## 10. Cycle Counting
|
||||
|
||||
### Cycle Accuracy Levels
|
||||
|
||||
| Level | Description |
|
||||
| -------------------- | -------------------- |
|
||||
| Functional | Correct results only |
|
||||
| Instruction-accurate | Fixed cycle counts |
|
||||
| Cycle-accurate | Page-cross penalties |
|
||||
|
||||
### Page Boundary Penalties
|
||||
|
||||
* Branch taken: +1 cycle
|
||||
* Branch crosses page: +2 cycles
|
||||
* Indexed load crosses page: +1 cycle
|
||||
|
||||
---
|
||||
|
||||
## 11. Known Hardware Quirks (NMOS 6502)
|
||||
|
||||
| Quirk | Description |
|
||||
| ---------------- | ------------------------------- |
|
||||
| JMP indirect bug | High byte wrap at page boundary |
|
||||
| BRK sets B flag | Only when pushed |
|
||||
| Unused flag bit | Always reads as 1 |
|
||||
|
||||
---
|
||||
|
||||
## 12. Illegal / Undocumented Opcodes (Optional)
|
||||
|
||||
* Many opcodes perform composite operations
|
||||
* Behavior varies by silicon revision
|
||||
* Should be disabled or explicitly enabled
|
||||
|
||||
---
|
||||
|
||||
## 13. Timing and Clocking
|
||||
|
||||
* One instruction executed per multiple clock cycles
|
||||
* Emulator may execute instructions per host tick
|
||||
* Cycle counter required for I/O timing
|
||||
|
||||
---
|
||||
|
||||
## 14. Integration with Peripherals
|
||||
|
||||
### Memory-Mapped I/O
|
||||
|
||||
```text
|
||||
if address in IO range:
|
||||
delegate to device
|
||||
```
|
||||
|
||||
Examples:
|
||||
|
||||
* 6522 VIA
|
||||
* UART
|
||||
* Video hardware
|
||||
|
||||
---
|
||||
|
||||
## 15. Testing and Validation
|
||||
|
||||
### Recommended Test ROMs
|
||||
|
||||
* Klaus Dormann 6502 functional tests
|
||||
* Interrupt and decimal mode tests
|
||||
|
||||
### Validation Checklist
|
||||
|
||||
* All instructions execute correctly
|
||||
* Flags match reference behavior
|
||||
* Vectors handled properly
|
||||
* Stack operations correct
|
||||
|
||||
---
|
||||
|
||||
## 16. Reference Links
|
||||
|
||||
* [https://www.masswerk.at/6502/6502_instruction_set.html](https://www.masswerk.at/6502/6502_instruction_set.html)
|
||||
* [https://www.nesdev.org/wiki/6502](https://www.nesdev.org/wiki/6502)
|
||||
* [https://github.com/Klaus2m5/6502_65C02_functional_tests](https://github.com/Klaus2m5/6502_65C02_functional_tests)
|
||||
* [https://en.wikipedia.org/wiki/MOS_Technology_6502](https://en.wikipedia.org/wiki/MOS_Technology_6502)
|
||||
|
||||
---
|
||||
|
||||
**Document Scope:** Software emulation of the 6502 CPU
|
||||
**Audience:** Emulator developers, retrocomputing engineers
|
||||
**Status:** Stable technical reference
|
||||
288
skills/legacy-circuit-mockups/references/emulator-6522.md
Normal file
288
skills/legacy-circuit-mockups/references/emulator-6522.md
Normal file
@@ -0,0 +1,288 @@
|
||||
# 6522 VIA (Versatile Interface Adapter) Emulation Specification
|
||||
|
||||
A technical Markdown specification for **emulating the MOS Technology / WDC 6522 VIA**, suitable for 6502-family emulators, SBC simulators, and retrocomputing software environments.
|
||||
|
||||
---
|
||||
|
||||
## 1. Scope
|
||||
|
||||
This document defines the functional behavior required to emulate:
|
||||
|
||||
* MOS Technology 6522 VIA
|
||||
* WDC 65C22 VIA (CMOS variant, where noted)
|
||||
|
||||
Out of scope:
|
||||
|
||||
* Analog electrical characteristics
|
||||
* Bus contention and propagation delay
|
||||
* Undocumented silicon race conditions
|
||||
|
||||
---
|
||||
|
||||
## 2. Chip Overview
|
||||
|
||||
### Core Features
|
||||
|
||||
| Feature | Description |
|
||||
| ---------------- | ------------------------------------ |
|
||||
| I/O Ports | Two 8-bit bidirectional ports (A, B) |
|
||||
| Timers | Two programmable timers |
|
||||
| Shift Register | 8-bit serial shift register |
|
||||
| Interrupt System | Maskable, prioritized |
|
||||
| Handshaking | CA1/CA2, CB1/CB2 control lines |
|
||||
|
||||
---
|
||||
|
||||
## 3. External Signals (Logical Model)
|
||||
|
||||
| Signal | Direction | Purpose |
|
||||
| -------- | --------- | ------------------------ |
|
||||
| PA0-PA7 | I/O | Port A |
|
||||
| PB0-PB7 | I/O | Port B |
|
||||
| CA1, CA2 | I/O | Control lines A |
|
||||
| CB1, CB2 | I/O | Control lines B |
|
||||
| IRQ | Output | Interrupt request to CPU |
|
||||
| CS1, CS2 | Input | Chip select |
|
||||
| R/W | Input | Read / write |
|
||||
| RS0-RS3 | Input | Register select |
|
||||
|
||||
---
|
||||
|
||||
## 4. Register Map
|
||||
|
||||
Registers are selected using RS3-RS0.
|
||||
|
||||
| Address | Name | R/W | Description |
|
||||
| ------- | ----------- | --- | -------------------------------- |
|
||||
| 0 | ORB / IRB | R/W | Output/Input Register B |
|
||||
| 1 | ORA / IRA | R/W | Output/Input Register A |
|
||||
| 2 | DDRB | R/W | Data Direction Register B |
|
||||
| 3 | DDRA | R/W | Data Direction Register A |
|
||||
| 4 | T1C-L | R | Timer 1 Counter Low |
|
||||
| 5 | T1C-H | R | Timer 1 Counter High |
|
||||
| 6 | T1L-L | W | Timer 1 Latch Low |
|
||||
| 7 | T1L-H | W | Timer 1 Latch High |
|
||||
| 8 | T2C-L | R | Timer 2 Counter Low |
|
||||
| 9 | T2C-H | R | Timer 2 Counter High |
|
||||
| 10 | SR | R/W | Shift Register |
|
||||
| 11 | ACR | R/W | Auxiliary Control Register |
|
||||
| 12 | PCR | R/W | Peripheral Control Register |
|
||||
| 13 | IFR | R/W | Interrupt Flag Register |
|
||||
| 14 | IER | R/W | Interrupt Enable Register |
|
||||
| 15 | ORA (no HS) | R/W | Output Register A (no handshake) |
|
||||
|
||||
---
|
||||
|
||||
## 5. Data Direction Registers
|
||||
|
||||
* Bit = 1 Output
|
||||
* Bit = 0 Input
|
||||
|
||||
```text
|
||||
output = ORx & DDRx
|
||||
input = external & ~DDRx
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 6. Port Behavior
|
||||
|
||||
### Read
|
||||
|
||||
* Returns input pins for bits configured as input
|
||||
* Returns output latch for bits configured as output
|
||||
|
||||
### Write
|
||||
|
||||
* Updates output latch only
|
||||
* Actual pin value depends on DDR
|
||||
|
||||
---
|
||||
|
||||
## 7. Timers
|
||||
|
||||
### Timer 1 (T1)
|
||||
|
||||
* 16-bit down counter
|
||||
* Can generate interrupts
|
||||
* Optional PB7 toggle
|
||||
|
||||
### Timer 2 (T2)
|
||||
|
||||
* 16-bit down counter
|
||||
* One-shot or pulse counting (CB1)
|
||||
|
||||
### Timer Emulation Rules
|
||||
|
||||
* Decrement once per CPU cycle
|
||||
* Reload from latch when appropriate
|
||||
* Set interrupt flag on underflow
|
||||
|
||||
---
|
||||
|
||||
## 8. Shift Register (SR)
|
||||
|
||||
Modes controlled via ACR:
|
||||
|
||||
* Disabled
|
||||
* Shift in under CB1 clock
|
||||
* Shift out under system clock
|
||||
|
||||
Emulator requirements:
|
||||
|
||||
* 8-bit shift
|
||||
* Correct bit order
|
||||
* Optional external clock handling
|
||||
|
||||
---
|
||||
|
||||
## 9. Control Registers
|
||||
|
||||
### Auxiliary Control Register (ACR)
|
||||
|
||||
Controls:
|
||||
|
||||
* Timer 1 mode
|
||||
* Timer 2 mode
|
||||
* Shift register mode
|
||||
* PB7 behavior
|
||||
|
||||
### Peripheral Control Register (PCR)
|
||||
|
||||
Controls:
|
||||
|
||||
* CA1/CB1 edge sensitivity
|
||||
* CA2/CB2 handshake / pulse / output modes
|
||||
|
||||
---
|
||||
|
||||
## 10. Interrupt System
|
||||
|
||||
### Interrupt Flag Register (IFR)
|
||||
|
||||
| Bit | Source |
|
||||
| --- | -------------------------- |
|
||||
| 0 | CA2 |
|
||||
| 1 | CA1 |
|
||||
| 2 | Shift Register |
|
||||
| 3 | CB2 |
|
||||
| 4 | CB1 |
|
||||
| 5 | Timer 2 |
|
||||
| 6 | Timer 1 |
|
||||
| 7 | Any interrupt (logical OR) |
|
||||
|
||||
### Interrupt Enable Register (IER)
|
||||
|
||||
* Bit 7 = set/clear mode
|
||||
* Bits 0-6 enable individual sources
|
||||
|
||||
### IRQ Logic
|
||||
|
||||
```text
|
||||
IRQ = (IFR & IER & 0x7F) != 0
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 11. Handshaking Lines
|
||||
|
||||
### CA1 / CB1
|
||||
|
||||
* Edge-detect inputs
|
||||
* Trigger interrupts
|
||||
|
||||
### CA2 / CB2
|
||||
|
||||
* Input or output
|
||||
* Pulse or handshake modes
|
||||
|
||||
Emulator must:
|
||||
|
||||
* Track pin state
|
||||
* Detect configured edges
|
||||
|
||||
---
|
||||
|
||||
## 12. Reset Behavior
|
||||
|
||||
On reset:
|
||||
|
||||
* DDRx = $00
|
||||
* ORx = $00
|
||||
* Timers stopped
|
||||
* IFR cleared
|
||||
* IER cleared
|
||||
* IRQ inactive
|
||||
|
||||
---
|
||||
|
||||
## 13. Read/Write Side Effects
|
||||
|
||||
| Register | Side Effect |
|
||||
| ----------- | ------------------------ |
|
||||
| ORA/ORB | Clears handshake flags |
|
||||
| T1C-H write | Loads and starts Timer 1 |
|
||||
| IFR write | Clears written bits |
|
||||
| IER write | Sets or clears enables |
|
||||
|
||||
---
|
||||
|
||||
## 14. Emulation Timing Levels
|
||||
|
||||
| Level | Description |
|
||||
| -------------- | ------------------------- |
|
||||
| Functional | Correct register behavior |
|
||||
| Cycle-based | Timers tick per CPU cycle |
|
||||
| Cycle-accurate | Matches real VIA timing |
|
||||
|
||||
---
|
||||
|
||||
## 15. Integration with 6502 Emulator
|
||||
|
||||
```text
|
||||
CPU cycle VIA tick update timers update IRQ
|
||||
```
|
||||
|
||||
* VIA must be clocked in sync with CPU
|
||||
* IRQ line sampled by CPU at instruction boundaries
|
||||
|
||||
---
|
||||
|
||||
## 16. Testing and Validation
|
||||
|
||||
### Recommended Tests
|
||||
|
||||
* VIA timer test ROMs
|
||||
* Port read/write tests
|
||||
* Interrupt priority tests
|
||||
|
||||
### Validation Checklist
|
||||
|
||||
* Timers count correctly
|
||||
* IRQ asserts and clears properly
|
||||
* DDR behavior correct
|
||||
* Side effects implemented
|
||||
|
||||
---
|
||||
|
||||
## 17. Differences: 6522 vs 65C22 (Summary)
|
||||
|
||||
| Feature | 6522 | 65C22 |
|
||||
| -------------- | ------ | -------- |
|
||||
| Power | Higher | Lower |
|
||||
| Decimal quirks | N/A | Fixed |
|
||||
| Timer accuracy | NMOS | Improved |
|
||||
|
||||
---
|
||||
|
||||
## 18. Reference Links
|
||||
|
||||
* [https://www.westerndesigncenter.com/wdc/documentation](https://www.westerndesigncenter.com/wdc/documentation)
|
||||
* [https://www.princeton.edu/~mae412/HANDOUTS/Datasheets/6522.pdf](https://www.princeton.edu/~mae412/HANDOUTS/Datasheets/6522.pdf)
|
||||
* [https://www.nesdev.org/wiki/6522](https://www.nesdev.org/wiki/6522)
|
||||
|
||||
---
|
||||
|
||||
**Document Scope:** Software emulation of the 6522 VIA
|
||||
**Audience:** Emulator developers, SBC designers
|
||||
**Status:** Stable technical reference
|
||||
233
skills/legacy-circuit-mockups/references/emulator-6C62256.md
Normal file
233
skills/legacy-circuit-mockups/references/emulator-6C62256.md
Normal file
@@ -0,0 +1,233 @@
|
||||
# AS6C62256 (32K x 8 SRAM) Emulation Specification
|
||||
|
||||
A technical Markdown specification for **emulating the AS6C62256 / 62256-family static RAM**, suitable for 6502-family emulators, SBC simulators, and memory subsystem modeling.
|
||||
|
||||
---
|
||||
|
||||
## 1. Scope
|
||||
|
||||
This document specifies functional behavior for emulating:
|
||||
|
||||
* Alliance Memory **AS6C62256**
|
||||
* Compatible **62256 (32K x 8) SRAM** devices
|
||||
|
||||
Out of scope:
|
||||
|
||||
* Analog electrical timing margins
|
||||
* Bus contention and signal rise/fall times
|
||||
* Power consumption characteristics
|
||||
|
||||
---
|
||||
|
||||
## 2. Chip Overview
|
||||
|
||||
### Core Characteristics
|
||||
|
||||
| Feature | Value |
|
||||
| -------------- | -------------------- |
|
||||
| Memory Type | Static RAM (SRAM) |
|
||||
| Capacity | 32,768 bytes (32 KB) |
|
||||
| Data Width | 8-bit |
|
||||
| Address Width | 15-bit (A0-A14) |
|
||||
| Access Type | Asynchronous |
|
||||
| Supply Voltage | 5 V (typical) |
|
||||
|
||||
---
|
||||
|
||||
## 3. External Signals (Logical Model)
|
||||
|
||||
| Signal | Direction | Purpose |
|
||||
| ------ | --------- | -------------------------- |
|
||||
| A0-A14 | Input | Address bus |
|
||||
| D0-D7 | I/O | Data bus |
|
||||
| CE# | Input | Chip enable (active low) |
|
||||
| OE# | Input | Output enable (active low) |
|
||||
| WE# | Input | Write enable (active low) |
|
||||
|
||||
> `#` indicates active-low signals.
|
||||
|
||||
---
|
||||
|
||||
## 4. Address Space Mapping
|
||||
|
||||
* Address range: `0x0000-0x7FFF`
|
||||
* Address lines select one byte per address
|
||||
|
||||
### Typical 6502 System Mapping Example
|
||||
|
||||
| CPU Address Range | Device |
|
||||
| ----------------- | -------------- |
|
||||
| `$0000-$7FFF` | AS6C62256 SRAM |
|
||||
| `$8000-$FFFF` | ROM / EEPROM |
|
||||
|
||||
---
|
||||
|
||||
## 5. Read and Write Behavior
|
||||
|
||||
### Read Cycle (Logical)
|
||||
|
||||
Conditions:
|
||||
|
||||
* `CE# = 0`
|
||||
* `OE# = 0`
|
||||
* `WE# = 1`
|
||||
|
||||
Behavior:
|
||||
|
||||
```text
|
||||
D[7:0] memory[A]
|
||||
```
|
||||
|
||||
If `OE# = 1` or `CE# = 1`, data bus is **high-impedance**.
|
||||
|
||||
---
|
||||
|
||||
### Write Cycle (Logical)
|
||||
|
||||
Conditions:
|
||||
|
||||
* `CE# = 0`
|
||||
* `WE# = 0`
|
||||
|
||||
Behavior:
|
||||
|
||||
```text
|
||||
memory[A] D[7:0]
|
||||
```
|
||||
|
||||
* `OE#` is ignored during writes
|
||||
* Write occurs on active WE#
|
||||
|
||||
---
|
||||
|
||||
## 6. Control Signal Priority
|
||||
|
||||
| CE# | WE# | OE# | Result |
|
||||
| --- | --- | --- | --------------- |
|
||||
| 1 | X | X | Disabled (Hi-Z) |
|
||||
| 0 | 0 | X | Write |
|
||||
| 0 | 1 | 0 | Read |
|
||||
| 0 | 1 | 1 | Hi-Z |
|
||||
|
||||
---
|
||||
|
||||
## 7. Emulator Interface Requirements
|
||||
|
||||
An emulator must expose:
|
||||
|
||||
```text
|
||||
read(address) -> byte
|
||||
write(address, byte)
|
||||
```
|
||||
|
||||
Internal storage:
|
||||
|
||||
```text
|
||||
uint8_t ram[32768]
|
||||
```
|
||||
|
||||
Address masking:
|
||||
|
||||
```text
|
||||
address = address & 0x7FFF
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 8. Timing Model (Abstracted)
|
||||
|
||||
### Emulation Levels
|
||||
|
||||
| Level | Description |
|
||||
| -------------- | ------------------------- |
|
||||
| Functional | Instantaneous access |
|
||||
| Cycle-based | Access per CPU cycle |
|
||||
| Cycle-accurate | Honors enable transitions |
|
||||
|
||||
For most systems, **functional emulation** is sufficient.
|
||||
|
||||
---
|
||||
|
||||
## 9. Power and Data Retention
|
||||
|
||||
* SRAM contents persist as long as power is applied
|
||||
* Emulator shall retain contents until explicitly reset
|
||||
|
||||
### Reset Behavior
|
||||
|
||||
* **No automatic clearing** on reset
|
||||
* Memory contents undefined unless initialized
|
||||
|
||||
---
|
||||
|
||||
## 10. Bus Contention and Hi-Z Modeling (Optional)
|
||||
|
||||
Optional advanced behavior:
|
||||
|
||||
* Track when SRAM drives the data bus
|
||||
* Detect illegal simultaneous writes
|
||||
|
||||
Most emulators may ignore Hi-Z state.
|
||||
|
||||
---
|
||||
|
||||
## 11. Error Conditions
|
||||
|
||||
| Condition | Emulator Response |
|
||||
| -------------------- | ----------------------------- |
|
||||
| Out-of-range address | Mask or ignore |
|
||||
| Read when disabled | Return last bus value or 0xFF |
|
||||
| Write when disabled | Ignore write |
|
||||
|
||||
---
|
||||
|
||||
## 12. Integration with 6502 Emulator
|
||||
|
||||
```text
|
||||
CPU memory access
|
||||
address decode
|
||||
if in SRAM range:
|
||||
AS6C62256.read/write
|
||||
```
|
||||
|
||||
* SRAM access is typically single-cycle
|
||||
* No wait states required
|
||||
|
||||
---
|
||||
|
||||
## 13. Testing and Validation
|
||||
|
||||
### Basic Tests
|
||||
|
||||
* Write/read patterns
|
||||
* Boundary addresses ($0000, $7FFF)
|
||||
* Randomized memory tests
|
||||
|
||||
### Validation Checklist
|
||||
|
||||
* Writes persist
|
||||
* Reads return correct values
|
||||
* Address wrapping correct
|
||||
|
||||
---
|
||||
|
||||
## 14. Common Mistakes
|
||||
|
||||
| Mistake | Result |
|
||||
| --------------------- | --------------------------- |
|
||||
| Clearing RAM on reset | Breaks software assumptions |
|
||||
| Wrong address mask | Mirrored memory errors |
|
||||
| Treating as ROM | Writes ignored |
|
||||
|
||||
---
|
||||
|
||||
## 15. Reference Links
|
||||
|
||||
* [Alliance Memory AS6C62256 Datasheet](https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf)
|
||||
* [https://en.wikipedia.org/wiki/Static_random-access_memory](https://en.wikipedia.org/wiki/Static_random-access_memory)
|
||||
|
||||
---
|
||||
|
||||
**Document Scope:** Software emulation of AS6C62256 SRAM
|
||||
**Audience:** Emulator developers, retro SBC designers
|
||||
**Status:** Stable technical reference
|
||||
266
skills/legacy-circuit-mockups/references/emulator-lcd.md
Normal file
266
skills/legacy-circuit-mockups/references/emulator-lcd.md
Normal file
@@ -0,0 +1,266 @@
|
||||
# DFRobot FIT0127 LCD Character Display Emulation Specification
|
||||
|
||||
## Overview
|
||||
|
||||
This document specifies how to **emulate the DFRobot FIT0127 LCD Character Display module**. FIT0127 is a **16x2 character LCD** compatible with the **HD44780 controller**, commonly used in 6502 and microcontroller breadboard systems.
|
||||
|
||||
The goal is **functional correctness** for SBC emulators, firmware testing, and UI visualization rather than electrical signal simulation.
|
||||
|
||||
---
|
||||
|
||||
## Module Summary
|
||||
|
||||
| Feature | Value |
|
||||
| ---------------- | ----------------------- |
|
||||
| Display Type | Character LCD |
|
||||
| Resolution | 16 columns x 2 rows |
|
||||
| Controller | HD44780-compatible |
|
||||
| Interface | 8-bit or 4-bit parallel |
|
||||
| Character Matrix | 5x8 dots |
|
||||
| Supply Voltage | 5V |
|
||||
|
||||
---
|
||||
|
||||
## Pin Definitions
|
||||
|
||||
| Pin | Name | Function |
|
||||
| ---- | ----- | ---------------- |
|
||||
| 1 | GND | Ground |
|
||||
| 2 | VCC | +5V |
|
||||
| 3 | VO | Contrast control |
|
||||
| 4 | RS | Register Select |
|
||||
| 5 | R/W | Read / Write |
|
||||
| 6 | E | Enable |
|
||||
| 7-14 | D0-D7 | Data bus |
|
||||
| 15 | A | Backlight + |
|
||||
| 16 | K | Backlight - |
|
||||
|
||||
---
|
||||
|
||||
## Logical Registers
|
||||
|
||||
| RS | Register |
|
||||
| -- | -------------------- |
|
||||
| 0 | Instruction Register |
|
||||
| 1 | Data Register |
|
||||
|
||||
---
|
||||
|
||||
## Instruction Set (Subset)
|
||||
|
||||
| Command | Code | Description |
|
||||
| --------------- | ----------- | ------------------------- |
|
||||
| Clear Display | `0x01` | Clears DDRAM, cursor home |
|
||||
| Return Home | `0x02` | Cursor to home position |
|
||||
| Entry Mode Set | `0x04-0x07` | Cursor direction |
|
||||
| Display Control | `0x08-0x0F` | Display, cursor, blink |
|
||||
| Cursor/Shift | `0x10-0x1F` | Shift cursor/display |
|
||||
| Function Set | `0x20-0x3F` | Data length, lines |
|
||||
| Set CGRAM Addr | `0x40-0x7F` | Custom chars |
|
||||
| Set DDRAM Addr | `0x80-0xFF` | Cursor position |
|
||||
|
||||
---
|
||||
|
||||
## Internal Memory Model
|
||||
|
||||
### DDRAM (Display Data RAM)
|
||||
|
||||
* Size: 80 bytes
|
||||
* Line 1 base: `0x00`
|
||||
* Line 2 base: `0x40`
|
||||
|
||||
Emulator mapping:
|
||||
|
||||
```text
|
||||
Row 0: DDRAM[0x00-0x0F]
|
||||
Row 1: DDRAM[0x40-0x4F]
|
||||
```
|
||||
|
||||
### CGRAM (Character Generator RAM)
|
||||
|
||||
* Stores up to 8 custom characters
|
||||
* 8 bytes per character
|
||||
|
||||
---
|
||||
|
||||
## Data Write Cycle
|
||||
|
||||
A write occurs when:
|
||||
|
||||
```
|
||||
RS = 1
|
||||
R/W = 0
|
||||
E: HIGH LOW
|
||||
```
|
||||
|
||||
### Emulator Behavior
|
||||
|
||||
* On falling edge of `E`, latch data
|
||||
* Write data to DDRAM or CGRAM depending on address mode
|
||||
* Auto-increment or decrement address based on entry mode
|
||||
|
||||
---
|
||||
|
||||
## Instruction Write Cycle
|
||||
|
||||
A command write occurs when:
|
||||
|
||||
```
|
||||
RS = 0
|
||||
R/W = 0
|
||||
E: HIGH LOW
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Read Cycle (Optional)
|
||||
|
||||
Reads are uncommon in hobby systems.
|
||||
|
||||
```
|
||||
RS = 0/1
|
||||
R/W = 1
|
||||
E: HIGH
|
||||
```
|
||||
|
||||
Emulator may simplify:
|
||||
|
||||
* Ignore reads entirely
|
||||
* Or return busy flag + address counter
|
||||
|
||||
---
|
||||
|
||||
## Busy Flag Emulation
|
||||
|
||||
### Real Hardware
|
||||
|
||||
* Busy flag = D7
|
||||
* Commands take 37-1520 µs
|
||||
|
||||
### Emulator Options
|
||||
|
||||
| Mode | Behavior |
|
||||
| ---------- | ----------------- |
|
||||
| Simplified | Always ready |
|
||||
| Timed | Busy for N cycles |
|
||||
|
||||
Recommended default: **Always ready**
|
||||
|
||||
---
|
||||
|
||||
## Power-Up State
|
||||
|
||||
On reset:
|
||||
|
||||
* Display OFF
|
||||
* Cursor OFF
|
||||
* DDRAM cleared or undefined
|
||||
* Address counter = 0
|
||||
|
||||
Emulator should:
|
||||
|
||||
* Clear DDRAM
|
||||
* Set cursor to (0,0)
|
||||
* Display enabled
|
||||
|
||||
---
|
||||
|
||||
## Cursor and Display Model
|
||||
|
||||
State variables:
|
||||
|
||||
```text
|
||||
cursor_row
|
||||
cursor_col
|
||||
display_on
|
||||
cursor_on
|
||||
blink_on
|
||||
```
|
||||
|
||||
Cursor moves automatically after writes based on entry mode.
|
||||
|
||||
---
|
||||
|
||||
## 4-bit vs 8-bit Interface
|
||||
|
||||
### 8-bit Mode
|
||||
|
||||
* Full byte transferred on D0-D7
|
||||
|
||||
### 4-bit Mode
|
||||
|
||||
* High nibble sent first
|
||||
* Two enable pulses per byte
|
||||
|
||||
Emulator simplification:
|
||||
|
||||
* Accept full byte writes
|
||||
* Ignore nibble timing
|
||||
|
||||
---
|
||||
|
||||
## Rendering Model (Emulator UI)
|
||||
|
||||
Recommended approach:
|
||||
|
||||
* Maintain 16x2 character buffer
|
||||
* Render ASCII subset
|
||||
* Substitute unsupported glyphs
|
||||
* Optionally render custom CGRAM chars
|
||||
|
||||
---
|
||||
|
||||
## Emulator API Model
|
||||
|
||||
```c
|
||||
typedef struct {
|
||||
uint8_t ddram[80];
|
||||
uint8_t cgram[64];
|
||||
uint8_t addr;
|
||||
bool display_on;
|
||||
bool cursor_on;
|
||||
bool blink_on;
|
||||
uint8_t entry_mode;
|
||||
} FIT0127_LCD;
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Common Wiring in 6502 Systems
|
||||
|
||||
```
|
||||
VIA Port LCD D4-D7 (4-bit mode)
|
||||
RS VIA bit
|
||||
E VIA bit
|
||||
R/W GND
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Testing Checklist
|
||||
|
||||
* Clear display command
|
||||
* Cursor positioning via DDRAM addresses
|
||||
* Sequential character writes
|
||||
* Line wrap behavior
|
||||
* Custom character display
|
||||
|
||||
---
|
||||
|
||||
## References
|
||||
|
||||
* [HD44780U Datasheet (Hitachi)](https://academy.cba.mit.edu/classes/output_devices/44780.pdf)
|
||||
* [Ben Eater LCD Interface Notes](https://hackaday.io/project/174128-db6502/log/181838-adventures-with-hd44780-lcd-controller)
|
||||
* [Ben Eater's 6502 Computer](https://github.com/tedkotz/be6502)
|
||||
* [Build a 6502 Computer](https://eater.net/6502)
|
||||
|
||||
---
|
||||
|
||||
## Notes
|
||||
|
||||
This spec intentionally prioritizes **firmware-visible behavior** over electrical accuracy, making it ideal for:
|
||||
|
||||
* SBC emulators
|
||||
* ROM and monitor development
|
||||
* Automated testing of LCD output
|
||||
* Educational CPU projects
|
||||
208
skills/legacy-circuit-mockups/references/lcd.md
Normal file
208
skills/legacy-circuit-mockups/references/lcd.md
Normal file
@@ -0,0 +1,208 @@
|
||||
# DFRobot FIT0127 LCD Character Display Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **DFRobot FIT0127** is a family of **HD44780-compatible character LCD modules** commonly used in embedded systems and hobbyist projects. These displays provide alphanumeric output using a dot-matrix character generator and support both 8-bit and 4-bit parallel interfaces.
|
||||
|
||||
FIT0127 modules are frequently paired with microcontrollers and 8-bit CPUs such as the **6502**, **AVR**, **PIC**, and **Arduino** platforms.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| ----------------- | --------------------------------------------------- |
|
||||
| Display type | Character LCD (STN, Yellow-Green backlight typical) |
|
||||
| Controller | HD44780 or compatible |
|
||||
| Interface | Parallel (4-bit or 8-bit) |
|
||||
| Character size | 5 x 8 dot matrix |
|
||||
| Operating voltage | 5 V logic (some variants support 3.3 V) |
|
||||
| Backlight | LED (separate power pins) |
|
||||
| Viewing mode | Transflective |
|
||||
|
||||
---
|
||||
|
||||
## 3. Display Variants
|
||||
|
||||
The FIT0127 designation is commonly associated with **16x2 character LCD modules**.
|
||||
|
||||
| Variant | Characters |
|
||||
| ------- | ------------------- |
|
||||
| FIT0127 | 16 columns x 2 rows |
|
||||
|
||||
---
|
||||
|
||||
## 4. Pin Configuration
|
||||
|
||||
### 4.1 Pinout (Standard 16-pin Header)
|
||||
|
||||
| Pin | Name | Description |
|
||||
| --: | ---- | --------------------- |
|
||||
| 1 | VSS | Ground |
|
||||
| 2 | VDD | +5 V supply |
|
||||
| 3 | VO | Contrast adjust |
|
||||
| 4 | RS | Register Select |
|
||||
| 5 | R/W | Read/Write select |
|
||||
| 6 | E | Enable |
|
||||
| 7 | D0 | Data bit 0 |
|
||||
| 8 | D1 | Data bit 1 |
|
||||
| 9 | D2 | Data bit 2 |
|
||||
| 10 | D3 | Data bit 3 |
|
||||
| 11 | D4 | Data bit 4 |
|
||||
| 12 | D5 | Data bit 5 |
|
||||
| 13 | D6 | Data bit 6 |
|
||||
| 14 | D7 | Data bit 7 |
|
||||
| 15 | A | Backlight Anode (+) |
|
||||
| 16 | K | Backlight Cathode (-) |
|
||||
|
||||
---
|
||||
|
||||
## 5. Electrical Characteristics (Typical)
|
||||
|
||||
| Parameter | Value |
|
||||
| ------------------- | ----------- |
|
||||
| Logic voltage (VDD) | 4.5 - 5.5 V |
|
||||
| Logic current | ~1-2 mA |
|
||||
| Backlight voltage | ~4.2 V |
|
||||
| Backlight current | 15-30 mA |
|
||||
|
||||
---
|
||||
|
||||
## 6. Interface Signals
|
||||
|
||||
### 6.1 RS (Register Select)
|
||||
|
||||
| RS | Function |
|
||||
| -- | -------------------- |
|
||||
| 0 | Instruction register |
|
||||
| 1 | Data register |
|
||||
|
||||
### 6.2 R/W
|
||||
|
||||
| R/W | Operation |
|
||||
| --- | ------------- |
|
||||
| 0 | Write to LCD |
|
||||
| 1 | Read from LCD |
|
||||
|
||||
### 6.3 Enable (E)
|
||||
|
||||
* Data is latched on the **falling edge** of E
|
||||
* E must be pulsed HIGH LOW for each transfer
|
||||
|
||||
---
|
||||
|
||||
## 7. Data Bus Operation
|
||||
|
||||
### 7.1 8-bit Mode
|
||||
|
||||
* Uses D0-D7
|
||||
* Faster operation
|
||||
|
||||
### 7.2 4-bit Mode
|
||||
|
||||
* Uses D4-D7 only
|
||||
* Data transferred in two nibbles (high first)
|
||||
* Saves I/O pins
|
||||
|
||||
---
|
||||
|
||||
## 8. Internal Memory Map
|
||||
|
||||
### 8.1 DDRAM (Display Data RAM)
|
||||
|
||||
| Address | Display Position |
|
||||
| --------: | ---------------- |
|
||||
| 0x00-0x0F | Line 1, Col 1-16 |
|
||||
| 0x40-0x4F | Line 2, Col 1-16 |
|
||||
|
||||
### 8.2 CGRAM (Character Generator RAM)
|
||||
|
||||
* Supports up to **8 custom characters**
|
||||
* Each character uses 8 bytes
|
||||
|
||||
---
|
||||
|
||||
## 9. Instruction Set (Summary)
|
||||
|
||||
| Instruction | Description |
|
||||
| ----------- | ---------------------- |
|
||||
| 0x01 | Clear display |
|
||||
| 0x02 | Return home |
|
||||
| 0x04-0x07 | Entry mode set |
|
||||
| 0x08-0x0F | Display on/off control |
|
||||
| 0x10-0x1F | Cursor/display shift |
|
||||
| 0x20-0x3F | Function set |
|
||||
| 0x40-0x7F | Set CGRAM address |
|
||||
| 0x80-0xFF | Set DDRAM address |
|
||||
|
||||
---
|
||||
|
||||
## 10. Initialization Sequence (4-bit Mode)
|
||||
|
||||
```text
|
||||
Wait >15 ms after VDD rises
|
||||
Function set: 0x33
|
||||
Function set: 0x32
|
||||
Function set: 0x28 (4-bit, 2-line)
|
||||
Display ON/OFF: 0x0C
|
||||
Entry mode: 0x06
|
||||
Clear display: 0x01
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 11. Timing Characteristics (Typical)
|
||||
|
||||
| Operation | Time |
|
||||
| ------------------ | -------- |
|
||||
| Enable pulse width | ≥ 450 ns |
|
||||
| Command execution | ~37 µs |
|
||||
| Clear / Home | ~1.52 ms |
|
||||
|
||||
---
|
||||
|
||||
## 12. Typical System Integration (6502 Example)
|
||||
|
||||
```text
|
||||
RS VIA output
|
||||
E VIA output
|
||||
D4-D7 VIA Port B
|
||||
R/W Grounded (write-only)
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 13. Contrast and Backlight Control
|
||||
|
||||
* Contrast adjusted via potentiometer on VO pin
|
||||
* Backlight may require series resistor
|
||||
* PWM dimming supported via external control
|
||||
|
||||
---
|
||||
|
||||
## 14. Absolute Maximum Ratings (Summary)
|
||||
|
||||
| Parameter | Rating |
|
||||
| -------------- | --------------------- |
|
||||
| VDD | -0.3 V to +6.0 V |
|
||||
| Input voltage | -0.3 V to VDD + 0.3 V |
|
||||
| Operating temp | -20 °C to +70 °C |
|
||||
|
||||
---
|
||||
|
||||
## 15. Common Use Cases
|
||||
|
||||
* Status displays
|
||||
* Debug output for SBCs
|
||||
* User interfaces for embedded systems
|
||||
* Retrocomputer front panels
|
||||
|
||||
---
|
||||
|
||||
## 16. References
|
||||
|
||||
* <https://static6.arrow.com/aropdfconversion/1f68489996f057bb6611f71d5fdb5f60f44faa72/pgurl_58439499065092.pdf>
|
||||
* <https://cdn.sparkfun.com/assets/9/5/f/7/b/HD44780.pdf>
|
||||
* <https://predictabledesigns.com/introduction-embedded-electronic-displays/>
|
||||
|
||||
---
|
||||
211
skills/legacy-circuit-mockups/references/minipro.md
Normal file
211
skills/legacy-circuit-mockups/references/minipro.md
Normal file
@@ -0,0 +1,211 @@
|
||||
# minipro Chip Programming Utility Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
**minipro** is an open-source, command-line utility used to **program, read, erase, and verify** a wide range of **EEPROM, Flash, EPROM, SRAM, GAL, and logic devices** using supported universal programmers such as the **T48**, **TL866II Plus**, and compatible models.
|
||||
|
||||
It is widely used in **Linux**, **macOS**, and **Windows** environments, especially for **retrocomputing**, **firmware development**, and **electronics prototyping**.
|
||||
|
||||
---
|
||||
|
||||
## 2. Supported Programmers
|
||||
|
||||
| Programmer | Notes |
|
||||
| ------------ | -------------------------- |
|
||||
| T48 | Full support (recommended) |
|
||||
| TL866II Plus | Full support |
|
||||
| TL866A / CS | Limited / legacy support |
|
||||
|
||||
---
|
||||
|
||||
## 3. Supported Device Types
|
||||
|
||||
### 3.1 Memory Devices
|
||||
|
||||
* Parallel EEPROM (e.g., AT28C256)
|
||||
* Flash memory (29xxx series)
|
||||
* EPROM (27xxx series)
|
||||
* SRAM (read/verify only)
|
||||
|
||||
### 3.2 Logic and PLDs
|
||||
|
||||
* GAL16V8 / GAL22V10
|
||||
* PAL devices (limited)
|
||||
|
||||
### 3.3 Other Devices
|
||||
|
||||
* Some microcontrollers (device-dependent)
|
||||
* Logic IC testing (selected models)
|
||||
|
||||
---
|
||||
|
||||
## 4. Installation
|
||||
|
||||
### 4.1 Linux
|
||||
|
||||
```bash
|
||||
sudo apt install minipro
|
||||
```
|
||||
|
||||
or from source:
|
||||
|
||||
```bash
|
||||
git clone https://github.com/vdudouyt/minipro.git
|
||||
make
|
||||
sudo make install
|
||||
```
|
||||
|
||||
### 4.2 Windows
|
||||
|
||||
* Install via MSYS2 or prebuilt binaries
|
||||
* Requires libusb driver (WinUSB)
|
||||
|
||||
---
|
||||
|
||||
## 5. Basic Command Syntax
|
||||
|
||||
```bash
|
||||
minipro [options]
|
||||
```
|
||||
|
||||
Common options:
|
||||
|
||||
| Option | Description |
|
||||
| ------------- | ---------------------- |
|
||||
| `-p <device>` | Select target device |
|
||||
| `-r <file>` | Read device to file |
|
||||
| `-w <file>` | Write file to device |
|
||||
| `-e` | Erase device |
|
||||
| `-v` | Verify contents |
|
||||
| `-I` | Device information |
|
||||
| `-l` | List supported devices |
|
||||
|
||||
---
|
||||
|
||||
## 6. Common Programming Operations
|
||||
|
||||
### 6.1 List Supported Devices
|
||||
|
||||
```bash
|
||||
minipro -l
|
||||
```
|
||||
|
||||
### 6.2 Identify Device
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -I
|
||||
```
|
||||
|
||||
### 6.3 Read a Chip
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -r rom_dump.bin
|
||||
```
|
||||
|
||||
### 6.4 Write a Chip
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -w rom.bin
|
||||
```
|
||||
|
||||
### 6.5 Verify Only
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -v rom.bin
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 7. Programming EEPROMs (AT28C256 Example)
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -w monitor.bin
|
||||
```
|
||||
|
||||
* Software Data Protection is handled automatically
|
||||
* Write cycle delays are internally managed
|
||||
* Verification performed after programming
|
||||
|
||||
---
|
||||
|
||||
## 8. Programming Flash Memory
|
||||
|
||||
```bash
|
||||
minipro -p SST39SF040 -e -w firmware.bin
|
||||
```
|
||||
|
||||
* Erase step required for Flash devices
|
||||
* Sector erase handled automatically
|
||||
|
||||
---
|
||||
|
||||
## 9. EPROM Operations
|
||||
|
||||
```bash
|
||||
minipro -p 27C256 -r eprom.bin
|
||||
```
|
||||
|
||||
* UV erase required before reprogramming
|
||||
* minipro verifies blank state before write
|
||||
|
||||
---
|
||||
|
||||
## 10. GAL Programming
|
||||
|
||||
```bash
|
||||
minipro -p GAL22V10 -w logic.jed
|
||||
```
|
||||
|
||||
* Uses JEDEC files
|
||||
* Supports read, write, and verify
|
||||
* Fuse maps viewable via `-I`
|
||||
|
||||
---
|
||||
|
||||
## 11. Error Handling and Messages
|
||||
|
||||
| Message | Meaning |
|
||||
| ---------------------- | -------------------------- |
|
||||
| `Device not found` | Incorrect device selection |
|
||||
| `Verification failed` | Data mismatch |
|
||||
| `Chip protected` | Write protection enabled |
|
||||
| `Overcurrent detected` | Insertion or wiring error |
|
||||
|
||||
---
|
||||
|
||||
## 12. Safety and Best Practices
|
||||
|
||||
* Always confirm device orientation in ZIF socket
|
||||
* Use correct device identifier (`-p`)
|
||||
* Do not hot-insert chips during operation
|
||||
* Use adapters for PLCC, SOP, TSOP packages
|
||||
|
||||
---
|
||||
|
||||
## 13. Typical Retrocomputing Workflow
|
||||
|
||||
1. Assemble ROM image
|
||||
2. Program EEPROM using minipro + T48
|
||||
3. Verify contents
|
||||
4. Install chip in SBC
|
||||
5. Test system boot
|
||||
|
||||
---
|
||||
|
||||
## 14. Limitations
|
||||
|
||||
* Not all devices are supported
|
||||
* Some microcontrollers require proprietary tools
|
||||
* In-circuit programming (ISP) not supported
|
||||
|
||||
---
|
||||
|
||||
## 15. References
|
||||
|
||||
* <https://gitlab.com/DavidGriffith/minipro>
|
||||
* <https://www.hadex.cz/spec/m545b.pdf>
|
||||
* <https://github.com/mikeroyal/Firmware-Guide>
|
||||
* <https://mike42.me/blog/2021-08-a-first-look-at-programmable-logic>
|
||||
* <https://retrocomputingforum.com/>
|
||||
|
||||
---
|
||||
174
skills/legacy-circuit-mockups/references/t48eeprom-programmer.md
Normal file
174
skills/legacy-circuit-mockups/references/t48eeprom-programmer.md
Normal file
@@ -0,0 +1,174 @@
|
||||
# T48 Universal EEPROM / Flash Programmer Specification
|
||||
|
||||
## 1. Overview
|
||||
|
||||
The **T48 Universal Programmer** (also sold as **TL866-3G / TL866II Plus successor**) is a USB-connected device used to **read, program, and verify** a wide range of **EEPROM, Flash, EPROM, GAL, and microcontroller devices**. It is commonly used in **retrocomputing**, **firmware development**, and **electronics repair** workflows.
|
||||
|
||||
The T48 is a modern replacement for the TL866 series, offering expanded device support and improved software compatibility.
|
||||
|
||||
---
|
||||
|
||||
## 2. General Characteristics
|
||||
|
||||
| Feature | Description |
|
||||
| ------------------- | ---------------------------------- |
|
||||
| Programmer type | Universal device programmer |
|
||||
| Interface | USB 2.0 |
|
||||
| Socket | ZIF-48 |
|
||||
| Supported devices | EEPROM, Flash, EPROM, GAL, MCU |
|
||||
| Programming voltage | Generated internally |
|
||||
| Host OS | Windows, Linux (open-source tools) |
|
||||
| Verification | Read-after-write, checksum |
|
||||
|
||||
---
|
||||
|
||||
## 3. Physical Description
|
||||
|
||||
### 3.1 ZIF Socket
|
||||
|
||||
* **48-pin Zero Insertion Force (ZIF)** socket
|
||||
* Supports DIP packages directly
|
||||
* PLCC, SOP, TSOP supported via adapters
|
||||
|
||||
### 3.2 Indicators and Controls
|
||||
|
||||
| Item | Description |
|
||||
| ------------- | --------------------------- |
|
||||
| Status LED | Power / activity indication |
|
||||
| ZIF lever | Locks IC into socket |
|
||||
| USB connector | Host connection and power |
|
||||
|
||||
---
|
||||
|
||||
## 4. Supported Device Categories
|
||||
|
||||
### 4.1 Memory Devices
|
||||
|
||||
* 27xxx EPROM
|
||||
* 28xxx EEPROM (e.g., AT28C256)
|
||||
* 29xxx Flash memory
|
||||
* Serial EEPROMs (with adapters)
|
||||
|
||||
### 4.2 Programmable Logic
|
||||
|
||||
* GAL16V8, GAL22V10 (read/write/verify)
|
||||
|
||||
### 4.3 Microcontrollers (Limited)
|
||||
|
||||
* Some PIC, AVR, and 8051-family devices
|
||||
* Programming support depends on voltage and pinout
|
||||
|
||||
---
|
||||
|
||||
## 5. Electrical Capabilities
|
||||
|
||||
| Parameter | Description |
|
||||
| -------------- | ---------------------------------------- |
|
||||
| VCC range | 1.8 V - 6.5 V (device dependent) |
|
||||
| VPP | Internally generated, device-specific |
|
||||
| I/O protection | Over-current and short-circuit protected |
|
||||
|
||||
---
|
||||
|
||||
## 6. Programming Operations
|
||||
|
||||
### 6.1 Common Operations
|
||||
|
||||
* Device identification
|
||||
* Blank check
|
||||
* Read
|
||||
* Program (write)
|
||||
* Verify
|
||||
* Erase (Flash/EPROM)
|
||||
|
||||
### 6.2 Verification Modes
|
||||
|
||||
* Byte-by-byte comparison
|
||||
* Checksum / CRC validation
|
||||
|
||||
---
|
||||
|
||||
## 7. Software Support
|
||||
|
||||
### 7.1 Official Software
|
||||
|
||||
* Windows-based GUI
|
||||
* Device database with pin mappings
|
||||
* Automatic voltage and timing control
|
||||
|
||||
### 7.2 Open-Source Tools
|
||||
|
||||
| Tool | Notes |
|
||||
| --------- | -------------------------------- |
|
||||
| `minipro` | Linux / macOS / Windows CLI tool |
|
||||
| libusb | USB communication backend |
|
||||
|
||||
Example:
|
||||
|
||||
```bash
|
||||
minipro -p AT28C256 -w rom.bin
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 8. Device Insertion and Pin Mapping
|
||||
|
||||
* Device orientation indicated by **pin 1 marker**
|
||||
* Many devices use **lower-left alignment** in ZIF socket
|
||||
* Software displays correct insertion diagram
|
||||
|
||||
---
|
||||
|
||||
## 9. Typical Workflow (EEPROM Example)
|
||||
|
||||
1. Select device type (e.g., AT28C256)
|
||||
2. Insert chip into ZIF socket
|
||||
3. Perform blank check
|
||||
4. Load binary image
|
||||
5. Program device
|
||||
6. Verify written contents
|
||||
|
||||
---
|
||||
|
||||
## 10. Power and Safety Notes
|
||||
|
||||
* Programmer powered entirely via USB
|
||||
* Do not insert or remove ICs while programming
|
||||
* Use adapters for non-DIP packages
|
||||
|
||||
---
|
||||
|
||||
## 11. Limitations
|
||||
|
||||
* Not all microcontrollers are supported
|
||||
* High-voltage EPROMs may require specific adapters
|
||||
* Not intended for in-circuit programming (ISP)
|
||||
|
||||
---
|
||||
|
||||
## 12. Common Use Cases
|
||||
|
||||
* Programming EEPROMs for 6502 SBCs
|
||||
* Flashing ROM images for retro systems
|
||||
* Reading and backing up legacy EPROMs
|
||||
* GAL logic development
|
||||
|
||||
---
|
||||
|
||||
## 13. Comparison with TL866II Plus
|
||||
|
||||
| Feature | TL866II Plus | T48 |
|
||||
| ----------------- | ------------ | --------------- |
|
||||
| Device support | Good | Expanded |
|
||||
| OS support | Windows | Windows / Linux |
|
||||
| Open-source tools | Limited | Excellent |
|
||||
|
||||
---
|
||||
|
||||
## 14. References
|
||||
|
||||
* <https://www.bulcomp-eng.com/datasheet/XGecu%20T48%20-%20Introduction.pdf>
|
||||
* <https://gitlab.com/DavidGriffith/minipro>
|
||||
* <https://opensource.com/article/23/1/learn-machine-language-retro-computer>
|
||||
|
||||
---
|
||||
Reference in New Issue
Block a user